Program Organizers: Jagdish Narayan, Dept of Matls Sci & Engrg, Box 7916, NC State University, Raleigh, NC 27695; John Sanchez, Advanced Micro Devices, M3 160, PO Box 3453, Sunnyvale, CA 94088
Wednesday, AM Room: Orange County 5
February 7, 1996 Location: Anaheim Marriott Hotel
Session Chair: J. Sanchez, Advanced Micro Devices, One AMD Place, Sunnyvale, CA 94088
8:30 am Invited
ALLOYING EFFECTS ON THE ELECTROMIGRATION BEHAVIOR IN NARROW Al INTERCONNECTS: O. Kraft, G. Bauer, E. Arzt, Max-Planck-Institut fur Metallforschung and Institit fur Metallkunde der Universitat Stuttgart, Seestrasse 92, 70174 Stuttgart, Germany
Al-based alloys are widely used in ULSI technology as interconnect materials. About 1 wt.% Cu is commonly added to the Al in conductor lines in order to improve the electromigration resistance. However, a satisfying interpretation of the mechanism by which Cu effects electromigration has not yet been given. Many other alloying additions have been investigated in the past without finding an alloy with further improved properties. In this paper, we present results of detailed analyses of electromigration-induced damage in lines of different alloys (pure Al, Al-Si-Cu, Al-Cu, and Al-Sc). These investigations reveal that the different additions influence the microstructure, and the mechanical and electronic properties of the material. A damage-based electromigration model is presented which takes these features into account and which is able to predict the electromigration-induced damage and the lifetime as a function of stress conditions. Finally, possible routes for the design of new alloys are outlined.
9:00 am Invited
ELECTROMIGRATION BEHAVIOR OF Cu(Sn) THIN FILM INTERCONNECTS: K .N. Tu, Department of Materials Science and Engineering, University of California, Los Angeles, CA 90095; K.L. Lee, C. K. Hu, IBM, T. J. Watson Research Center, PO Box 218, Yorktown Heights, NY 10598
In- situ SEM has been used for real time comparison studies of the electromigration behavior of Cu and Cu- 0.5 to 2 wt.% Sn alloy thin film interconnects. Drift velocity test structures were powered at current density of 5 x 105 to 2.1 x 106 amp/cm2 over the temperature range of 250 to 450deg.C. The measured electromigration activation energy for Cu and Cu (Sn) alloys are 0.73 eV and 0.95 to 1.25 eV, respectively. The measured resistivity values of the Cu- 0.5 wt.% Sn and Cu- 1 wt.% Sn alloys are 2.4 and 2.9 - cm, respectively. These characteristics show that Cu (Sn) alloys are potentially good candidates for future interconnect metallization where high conductivity and good electromigration resistance are required.
9:30 am Invited
STRESS AND ELECTROMIGRATION IN THIN FILM CONDUCTORS: J. R. Lloyd, Digital Equipment Corporation, 77 Reed Road, Hudson, MA 01749; M. A. Korhonen, Dept. Materials Science and Engineering, Cornell University, Ithaca, NY 14853
Electromigration failure, due to a divergence in the mass flux responding to current flow, is significantly affected by stress and stress gradients. These gradients are caused by electromigration itself and, for instance, by thermal history and the choice of and process used to deposit interlevel dielectric materials and passivation layers. The time to failure can be treated as the time necessary to reach a critical stress or a critical vacancy/atomic concentration to form a void or an extrusion. Whether the process is best described as the diffusion of vacancies, atoms or stress will be discussed. The interaction of electromigration induced and other stresses in the conductor will be explored.
10:00 am BREAK
A VIA SHORTING MECHANISM RELATED TO THE ROUGHNESS OF THE METAL LAYERS: J. Maniaci, N. de Lanerolle, Standard Microsystems Corporation, 35 Marcus Blvd., Hauppauge, NY 11788
Excessive failures due to electrical shorts were experienced in via contacts between the first level metal layers (M1) and the second level metal layers (M2). Scanning electron micrograph studies showed holes in the interlevel dielectric on completed wafers using decorative wet etching technique. Holes were caused by particles and possibly hillocks protruding through the photoresist and being cut off by plasma etch erosion of the resist. High particle counts in the underlying layer in M1 exacerbated the problem. If alloying is performed after the interlevel dielectric deposition the via contact resistance was lowered. In this case, profilometric measurements showed a decrease in roughness of the second level metal layer (M2). It is proposed that there is a relationship between increased roughness, and susceptibility to electrical shorts and increased contact resistance.
MICROSTRUCTURE MAPPING OF INTERCONNECTS USING ORIENTATION IMAGING MICROSCOPY: David J. Dingley, D. P. Field, TSL Inc., 226 West 2230 North Provo, UT 84604; H. H. Wills Physics Laboratory, University of Bristol, Bristol BS8 1TL, UK
The new technique of Orientation Imaging Microscopy, OIM, provides a detailed description of the variation in crystallography over the surface of single crystal or polycrystalline bulk materials. This technique has been used in the investigation of interconnect lines and contact pad material in a number of aluminum metallizations on silicon oxide/silicon substrates. The specimens were examined in a SEM fitted with the OIM system. The technique has provided information regarding the local texture variations between the different regions of a metallized silicon wafer between contact pad and interconnect line. It could be concluded that significant modification of the microstructure had occurred subsequent to initial metal deposition and that this modification differed between contact pad and interconnect line.
THE EFFECTS OF DEPOSITION CONDITIONS ON THE CRYSTALLOGRAPHIC TEXTURE OF SPUTTERED Ti, TiN and Al ALLOY THIN FILMS: Paul R. Besser, J.E. Sanchez, Jr., Advanced Micro Devices, One AMD Place, Sunnyvale, CA 94088; D. Knorr, Materials Engineering Department, Rensselaer Polytechnic Institute, Troy, NY 12180-3590
Abstract not available.
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