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1997 TMS Annual Meeting: Monday Session


Sponsored by: MSD Flow and Fracture; SMD Mechanical Metallurgy; EMPMD Electronics Packaging and Interconnection Materials Committees
Program Organizers: R.K. Mahidhara, Tessera Inc., 3099 Orchard Drive, San Jose, CA 95134; D.R. Frear, Sandia National Laboratory, Mail Stop 1411, Albuquerque, NM 87185; S.M.L. Sastry, Washington University, Mechanical Engineering Dept., St. Louis, MO 63130; K.L. Murty, North Carolina State University, Materials Science and Engineering Dept., Box 7909, Raleigh, NC 27695; P.K. Liaw, University of Tennessee, Materials Science and Engineering Dept., Knoxville, TN 37996; W.L. Winterbottom, Reliability Consultant, 30106 Pipers Lane Court, Farmington Hill, MI 48331

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Room: 332

Session Chairperson: Ephraim Suhir, Lucent Technologies, Bell Laboratories, Room 7G-326, 700 Mountain Avenue, NJ 07974; Theodore Ejim, Lucent Technologies, Bell Laboratories, Engineering Research Center, P.O. Box 900, Princeton, NJ 08542

8:30 am

OPENING STATEMENTS: Dr. Darrel R. Frear, EMPMD Chair and, Senior Member of Technical Staff, Department 1811, Mail Stop 1411, P.O. Box 5800, Sandia National Laboratories, Albuquerque, NM 87185

8:40 am KEYNOTE

MICROELECTRONIC PACKAGE TRENDS--THE ROLE OF RELIABILITY IN PARTICULARLY, RELATED TO SOLDER JOINT RELIABILITY: C.P. Wong* and Rao Tummala**, Georgia Institute of Technology, Packaging Research Center (PRC), School of Materials Science & Engineering, and School of Electrical & Computer Engineering, 778 Atlantic Drive, Atlanta, GA 30332;*Professor and Assistant Director, PRC; **Pettit Chair Professor, Georgia Eminent Scholar and Director, PRC

The trends of microelectronic devices have advanced to the state that they operate in excess of 200 MHz with submicron feature size. Furthermore, these high performance IC requires Inputs/Outputs (I/O) signals that are in excess of a few 1000's. Low-cost, high performance flip-chip, area array solder joint interconnects are key to the success of this technology. In order to enhance the thermal cycle fatigue-life of these solder joints, underfill encapsulants are needed. In this talk, we will review the microelectronic packaging technology trends, the role of reliability, in particularly, the use of underfill encapsulants to enhance the thermal cycle fatigue life of solder joints will be discussed.

9:15 am KEYNOTE

SOLDER JOINTS IN ELECTRONICS--DESIGN FOR RELIABILITY: Werner Engelmaier, President, Engelmaier Associates, Inc., 23 Gunther Street, Mendham, NJ 07945

The emerging new technologies provide ever more challenges to assure the reliability of electronic products. The ever increasing demands in electronic products for higher performance, lower cost, less space (weight) is leading to ever denser interconnection needs. Solder joint reliability is becoming an even more important issue with the advent of new surface mount packages and the use of surface mounted electronics in such hostile environments as the automobile and space. The new packages are characterized by larger sizes, finer pitches, and/or problematic materials which require an up-front 'Design for Reliability (DfR)' to meet reliability requirements. The hostile environments can include thermal excursions over temperature ranges in which multiple interactive damage mechanisms are operative. The reliability of electronic assemblies requires a definitive design effort that has to be carried out concurrently with the other design functions during the developmental phase of the product. There exists a misconception in the industry, that quality manufacturing is all that is required to assure the reliability of an electronic assembly. While of course, consistent high quality manufacturing - and all that this implies is a necessary prerequisite to assure the reliability of the product, only a DfR-procedure can assure that the design - manufactured to good quality - will be reliable in its intended application. Explicit DfR-procedures need to be employed to account and compensate, at least in part, for the prevalent damage mechanisms. This needs to be complemented with 'Design for Manufacturability (DfM)' which widens the process windows and takes into account the manufacturing capabilities. These demands put an increasing burden on the designers who will require a heightened technical understanding of the underlying issues and more sophisticated design tools. Thus, adherence to quality standards, such as IPC-A-620, Acceptability of Electronic Assemblies with Surface Mount Technologies, and ANSI/J-STD-001, Requirements for Soldered Electrical and Electronic Assemblies does not assure reliable solder connections, only quality solder connections. It is for this reason that IPC-D-279, Design Guidelines for Reliable Surface Mount Technology Printed Board Assemblies, is being developed. The 'Design for Reliability (DfR)' for solder attachments in electronic interconnections will be the emphasis of the paper.

9:50 am KEYNOTE

MEETING MARKET DEMANDS--NEW AND CRITICAL TECHNOLOGIES FOR ELECTRONIC PACKAGING AND ASSEMBLIES: Jennie S. Hwang, President, H-Technologies Group Inc., 5325 Naiman Parkway, Cleveland, OH 44139

Advanced technologies are transforming manufacturing, and the information highway is speedily progressing. In this exciting and changing time, the electronic industry has responded and will continue to respond to competitive products in the global market place. The speaker will provide a capsule view of key segments of electronics hierarchy in market needs and the demands in new technologies. The presentation will separately address the market and technology in chip level, package level, and board level, as well as, the critical supporting materials and technologies. Dr. Hwang will conclude her talk by highlighting the important aspects of the reliability of solder joints in relation to the new market trends.

10:25 am BREAK

10:35 am INVITED

SOLDER MATERIALS AND SOLDER JOINTS IN FIBER OPTICS ENGINEERING--RELIABILITY REQUIREMENTS AND PREDICTED STRESSES: Ephraim Suhir, Lucent Technologies, Bell Laboratories, Physical Sciences and Engineering Division, Room 7G-326, 700 Mountain Avenue, NJ 07974

Typical solder materials and solder joints, employed in fiber-optics engineering, are examined from the stand-point of the requirements for optical performance of the devices, as well as for the short- and long term mechanical reliability of the soldered optical fibers and the solder materials themselves. We address the geometry's of, and the loading condition in, fiber-optics solder joints, and suggest several analytical stress models that enable one to evaluate thermally and mechanically induced stresses in solder joint assemblies in fiber-optics structures. These models include: thermal stresses in metallized fibers soldered into ferrules or capillaries; stresses at the menisci areas in soldered joints; comparison of the thermal stresses due to the application of "hard" (high modulus) and "soft" (low modulus) solders; interaction of the "global" and "local" thermal stresses in optical fibers whose end portions are soldered into capillaries; evaluation and interaction of mechanical and thermal stresses in solder joints during proof-testing of optical fibers soldered into ferrules; and others. The merits and shortcomings of soldered assemblies in comparison with adhesively bonded structures are also briefly discussed.

11:00 am INVITED

MICROSTRUCTURAL ANALYSIS OF ELECTRONIC MATERIALS: Aleksander Zubelewicz, IBM Microelectronics, W-64, Bldg. 4-2, 1701 North Street, Endicott, NY 13760

The electronic industry is changing at a rapid pace. Faster and more powerful processors and ASICs continuously replace the slower devices, while price competitiveness and time-to-market becomes the true challenge for many manufacturers. The dynamic nature of the electronic industry drives for the need of using smaller packages with higher I/O count. Recently, fine pitch, a family of BGA components, and Chip Scale Packages represent the "hottest" technologies allowing for high I/O density. However, the future electronics applications will require processors operating with speed of several hundred MHz, then the present packaging technology may need further modifications. Consequently, the traditional PTH interconnection technology is being replaced by Surface Mount Technology and Ball Grid Arrays. Furthermore, new interconnection materials such as lead free solders and conductive adhesives are being seriously considered as a replacement of the commonly used lead based alloys. The objective of the paper is to discuss the behavior and failure mechanisms for the interconnection materials. Obviously, solders are at the top of the list, followed by encapsulations and conductive adhesives. During manufacturing operations, solders are used in the form of a paste, and when reflowed becomes ductile polycrystalline materials. These pastes must maintain appropriate rheological characteristics. It will be shown that a typical paste (solder or conductive adhesive) exhibits three stages of behavior: paste as a viscous solid, paste as a viscous fluid, and the transition stage between solid and fluid. Solder joints (after reflow) are thought to carry input/output electrical functions of the assembly as well as are designed to provide a mechanical support for the package or chip. Solders exhibit very complex microstructural behavior. There is a need for material model of solders, a model that can be used in the form of constitutive equations with built-in damage criteria, equipped with functions that represent microstructural evolution of solders, and allowing to predict the effect of strain/damage localization in solder joints. Moreover, this theory should lead to simple fatigue equations when needed. One such theory exists and will be discussed in the paper. In many cases, solder joints become the weakest link. Enhancement of the joint reliability can be accomplished by encapsulating them with polymer based materials. A microstructural numerical study for encapsulant will be briefly presented in the paper. It will be shown that fracture originates at the microscopic level of the materials, coalesce, and forms a localized fracture zone.

11:25 am INVITED

INCONSISTENCIES IN THE UNDERSTANDING OF SOLDER JOINT RELIABILITY PHYSICS: Liang-chi Wen, G. Mon, R. Ross, Jr., Jet Propulsion Laboratory, California Institute of Technology, 4800 Oak Grove Drive, Pasadena, CA 91109

An inherent reliability problem associated with surface mount applications is that solder joints, which serve both as an electrical and a mechanical connection between part and board, are subject to thermal fatigue failure. Solder joint failure involves a complex interplay of creep and fatigue processes. Over the years, many analytical and experimental research studies have aimed to improve state-of-the-art assessment of solder joint integrity from a physics of failure perspective. Although considerable progress has been made, there still exist many inconsistent and even contradictory correlations and conclusions. This paper reviews the unique properties of near-eutectic tin-lead solder, properties such as age-softening and 'superplastic' behavior under low strain rate loading. Fundamental mechanical and thermomechanical processes are modeled to demonstrate many inconsistencies observed in the literature. These inconsistencies are to be found in both analysis and testing issues. Analytical inconsistencies arise in correlations involving Coffin-Manson and strain energy density algorithms for cycle-life prediction, the effects of mean temperature and cycle frequency, and the determination of test acceleration factors. Testing inconsistencies are to be found in the areas of mechanical versus thermal cycling, failure definations, detection methodology and treatment of failure statistics. The objective of this paper is to identify important unsettled analysis and testing issues whose resolution by the solder joint research community will assure a greater degree of solder joint reliability.

11:50 am INVITED

AUTOMATED SOLDER LIFE ANALYSIS OF ELECTRONIC MODULES: Stephen A. McKeown, Lockheed Martin Control Systems, 600 Main Street, Johnson City, NY 13790

The solder life analysis methods developed by Engelmaier and Steinberg have been incorporated into an automated method which combines the results of finite-element models, a component location file obtained from a computer-aided design tool, component data, and environment data to calculate the expected solder joint life for each surface mount technology component on an electronic module. The method uses the finite-element method to calculate the coefficient of thermal expansion at different locations on the surface of the module which is used in determining the thermal cycling life of the solder joints. Finite-element analysis is also used to determine the surface strains due to vibration of the module which also influences solder joint life. The component location is taken from a Mentor® neutral file which also provides component description and orientation. Component data includes the dimensions of the part and information on the solder joint fillet geometry. Environment data includes temperature ranges, dwell times, vibration levels, and durations of thermal/vibration missions. This information is combined in a ANSI C-language program to determine the calculated failure rate of each component for the combined environments, and the overall computed reliability of all of the analyzed solder joints.

12:10 am


The Coffin-Manson approach is based on relating fatigue life to plastic strain range. The basic equation has been modified by Norris-Landzberg, Engelmaier, and others to include temperature, frequency or dwell time effects. These modifications were determined empirically on specific types of soldered assemblies. Today, they are commonly applied to a wide range of assemblies and test conditions, as well as field use conditions. The main advantage of these empirical relations is that they are easy to use. They are basically back of the envelope calculations that require almost no expertise on the part of the engineer. This paper explores the validity of modified Coffin-Manson approaches as applied to solder joint reliability analysis. Several case studies are examined, and the limits of the approach are defined.

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