The following sessions are among those that will be held during the 39th Electronic Materials Conference (EMC) on Wednesday afternoon, June 25, at Colorado State University, Fort Collins, Colorado. To view the other Wednesday afternoon sessions as well as other programming planned for the meeting, go to the EMC Calendar of Events.
CHAIR: Russ Dupuis, Microelectronics Research Center, University of Texas, Austin, TX 78712
CO-CHAIR: Diego Olego, Philips Research, Briarcliff Manor, NY 10510
1:30 pm, Invited
Dislocation Generation and Reduction in GaN Heteroepitaxy: J.S. Speck, X.H. Wu, P. Fini, E.J. Tarsa, Y. Golan, D. Kapolnek, S. Keller, U.K. Mishra and S.P. Denbaars, University of California, Santa Barbara, CA 93106
Experimental results and models are presented for the mechanisms of threading dislocation (TD) generation and reduction in GaN growth on sapphire. This work is motivated by recent results that suggest at high TD densities (e.g., ~1010 cm-2), the TDs may strongly contribute to carrier scattering. Recent results from Hewlett-Packard Laboratories have demonstrated that TDs in GaN behave a non-radiative recombination centers. The optimal nucleation layers (NLs) for achieving low TD density material (mid-108 cm-2 and lower) (with high electron mobility, >700 cm2/Vs at 298 K, and strong PL) consist of mixed cubic/hexagonal GaN, which sustains its stacking disorder and island-like morphology after heating to HT. The HT growth proceeds by the formation of coarse islands which then coalesce. The HT island coalescence is accompanied by rapid surface smoothing. Isolated HT islands generally contain a small number of mixed or pure screw character TDs, whereas the majority of the edge TDs are generated at island coalescence. Under optimal conditions, a total TD density of ~5x108 cm-2 can be achieved. Using identical NLs ("Material A" conditions in our previous reports), controlling the HT growth conditions can markedly change the HT island nucleation density and lead to changes in the TD density by as much as two orders of magnitude (this in contrast to our previous reports that demonstrated that extensive nitridation of the sapphire substrate, "Material B" conditions, also strongly impacts the total TD density). These results offer possible routes for further reduction in the TD density in GaN heteroepitaxy on dissimilar, large mismatch substrates such as sapphire and MgAl2O4 spinel. We present dislocation-based models to the TD generation and evolution, for which the essential features have been verified by TEM and AFM studies. The stacking disorder and mosaic between the NL and HT GaN is accommodated by Frank and Shockley partial dislocations. The dislocation lines for these partial dislocations remain in the (0001) plane and thus do not generate TDs. Regions of the NL that have coalesced and transformed to hexagonal GaN are a source of TDs in the HT GaN. These results are consistent with our NL studies: optimal Material A NLs are highly faceted, mixed cubic/hexagonal GaN and just cover the sapphire substrate. Finally, recent we present experimental results on the relationship between extended defect generation in the HT GaN layer and the sapphire surface preparation.
Effect of the Growth Ambient on the Electrical and Optical Properties of GaN and InGaN Films Grown by MOCVD: S. Keller, A.C. Abare, M.P. Mack, D. Kapolnek, L.A. Coldren, U.K. Mishra and S.P. DenBaars, Electrical And Computer Engineering and Materials Departments, University of California, Santa Barbara, CA 93106
Recently, the material system (In,Ga)N has gained much interest due to its application for optoelectronic devices operating in the visible range of the electromagnetic spectrum. In this paper we studied the influence of the carrier gases nitrogen and hydrogen and their mixtures on the electrical and optical properties of GaN and InGaN films grown by atmospheric pressure MOCVD in the temperature range from 750 to 1050°C. At low deposition temperatures, GaN films of comparable quality to those deposited at 1050°C were obtained by carefully adjusting the V/III ratio during growth. GaN films grown in nitrogen were characterized by a lower free carrier concentration than GaN films grown in hydrogen for growth performed at 1050°C as well as at 810°C. Photoluminescence measurements performed at 22 K showed a full width at half maximum of the band edge related luminescence of 4.67 meV for films grown in N2 and 6.83 meV for layers grown in H2 at 810°C. The free carrier concentration of the same samples was 5x1016 and 1x1018cm-3, respectively. In the case of InGaN, the partial pressure of H2 in the system had a strong effect on both, the indium incorporation efficiency and the electrical and optical properties of the films. Thus, the admixture of H2 resulting in a partial pressure as little as 5x10-3 atm caused the indium incorporation to drop by a factor of 0.6 compared to a film grown entirely in N2. However, films grown without addition of an H2 were insulating and showed pronounced deep level related luminescence. The amount of H2 necessary to obtain films showing n-type conductivity and predominantly band edge related luminescence increased with decreasing growth temperature. Possible mechanisms causing this behaviour will be discussed. The optimum growth conditions for GaN and InGaN were chosen for the growth of InGaN/GaN MQW structures. Internal quantum efficiency measurements revealed a value higher than 56% for the best samples.
2:30 pm, Student Paper
Growth and Characterization of Mg-Doped GaN Epitaxial Layers: C.J. Eiting, P.A. Grudowski, J. Park, B.S. Shelton, D.J.H. Lambert and R.D. Dupuis, Microelectronics Research Center, University of Texas at Austin, Austin, TX 78712-1100
The growth of high-conductivity p-type GaN films is of critical importance for many InAlGaN devices. In this talk, data are presented on the growth of p-type Mg-doped GaN epitaxial layers and p-n junctions by low-pressure metalorganic chemical vapor deposition. The structures are grown at 76-200 Torr on sapphire substrates using trimethlgallium (TMGa), triethylgallium (TEGa), biscyclopentadienylmagnesium (Cp2Mg), and ammonia (NH3). The Mg incorporation is found to strongly depend upon growth temperature and total reactor chamber pressure, as well as upon the [Cp2Mg]/[Ga precursor] molar flow ratio. The choice of the gallium precursor is also shown to have an effect on Mg incorporation. The effect of the V/III ratio has also been explored. The films have been characterized by room-temperature (300K) and low-temperature (4.2K) photoluminescence (PL), variable-temperature Hall-effect measurements, secondary-ion mass spectroscopy (SIMS), X-ray diffraction, and secondary-electron and Nomarski microscopy. At a fixed growth temperature, the free-hole concentration of these GaN:Mg layers is shown to saturate at relatively low Cp2Mg molar flows (i.e. p=1x1017 cm-3 at [Cp2Mg]=1-2µmole/min). At higher [Cp2Mg], the layers become more resistive and the hole concentration decreases. The surface morphology of the films degrades with increased Cp2Mg molar flows and decreased growth temperatures. PL spectra from these GaN:Mg layers correlate well with Hall-effect data. High-intensity, donor-acceptor-related 300K PL emission at ~440nm is observed from high hole concentration, low-resistivity films. In addition, a strong dependence of PL characteristics, especially the intensity, upon the Mg-activation anneal conditions is observed. In addition, we have studied the "memory effect" produced by using Cp2Mg as a dopant source. SIMS data from GaN p-n and n-p-n structures confirm the sharp turn-on and turn-off characteristics of the Mg dopant, and verify the junction depth of GaN:Mg/GaN:Si homojunctions. Finally, we will discuss the growth of abrupt p-n junction profiles and the I-V characteristics of these junctions. *Work supported in part by DARPA, Ford Motor Co., NSF, ONR and The State of Texas.
2:50 pm, Student Paper
Multi-Step Growth Approach for GaN over Layers Grown by MOCVD: J.T. Kobayashi, N.P. Kobayashi and P.D. Dapkus, Compound Semiconductor Laboratory, Department of Material Science and EE/Electrophysics, University of Southern California, Loss Angeles, CA 90089-0271; S. Zhang and D.H. Rich, Photonic Materials and Devices Laboratory, Department of Materials Science and Engineering, University of Southern California, Los Angeles, CA 90089-0241; S. Kim and S.G. Bishop, Microelectronics Laboratory, Department of Electrical and Computer Engineering, University of Illinois-Urbana, Urbana, IL 61801
The growth behavior of GaN grown on (0001) sapphire substrates by atmospheric pressure metalorganic chemical vapor deposition (MOCVD) in a closed space showerhead reactor has been studied. Three distinct growth stages, (1) nucleation of truncated three-dimensional islands (TTIs), (2) merging of TTIs, and (3) two dimensional growth after complete merging of TTIs, are observed. To minimize the thermal desorption and mass transport of a low temperature (450°C) buffer layer during the growth of GaN overlayer at higher temperature (900-1050°C) in our work, a second buffer layer is grown at an intermediate temperature (800°C). We have found this buffer layer strategy to be essential to effect rapid lateral growth and merging of the TTI and subsequent two dimensional growth. The growth of a low temperature buffer layer has been demonstrated by many workers as being essential to the growth of smooth continuous films of GaN on sapphire. We have observed that the subsequent growth of layers at higher temperatures is strongly effected by the evolution of the dense nuclei nuclei formed at this stage. Growth at higher temperatures on this buffer results in the formation of three dimensional islands truncated by the (0001) plane and with a preferred orientation. These are formed by the redistribution of material in the buffer layer and by deposition of materials. We have found that it is desirable to foster as dense of nucleation of these islands as possible and to promote three dimensional growth until the islands merge. This is aided by growth at 800°C - a temperature low enough to increase the layer thickness and apparently to favor the preferred nuclei. Then the lateral growth rate must be increased by increasing growth temperature to complete merging of TTIs and make growth mode two dimensional growth mode. The growth temperature at each stage is important since temperatures too high will result in desorption and redistribution of the buffer layers and less dense nucleation. Therefore we have introduced a multi-step growth approach, in which the growth conditions are changed at each evolution stage. By using this multi-step growth approach, we obtained colorless films with featureless morphology. These films have excellent optical properties. The ratio of near band edge emission to yellowband emission measured by photoluminescence at 6K is as high as 1764. The talk will describe the evolution of these stages and the reasons for our choice of this approach. We will also present both PL and CL characterization of the properties of films grown under various conditions. Furthermore we will describe the continuous two dimensional growth and properties of GaN on these featureless surfaces of GaN and the effect of the growth conditions on the properties of the films. This will include a discussion of the conditions necessary to maintain a two dimensional growth mode while at the same time achieving good PL and transport properties.
3:10 pm, Break
Lateral Epitaxial Overgrowth of GaN Layers on SiO2 via OMVPE: O.-H. Nam, M.D. Bremser, T. Zheleva and R.F. Davis, Department of Materials Science and Engineering, North Carolina State University, PO Box7907, Raleigh, NC 27695-7907
Gallium nitride films have been achieved via lateral coalescence of GaN islands obtained using low pressure organometallic vapor phase epitaxy within circular holes contained in 100 nm thick patterned SiO2 layers. Each multilayer structure on which the final GaN layer was deposited consisted of a 6H-SiC(0001) substrate, a 100 nm AlN buffer layer, a 1.5 µm thick GaN film and the patterned SiO2 layer. The patterning of the SiO2 layer was achieved using standard lithography and chemical etching. Transmission electron microscopy revealed that the laterally overgrown portions of the GaN layers contained much lower densities of line and planar defects than the traditional films grown directly on GaN or AlN buffer layers on either sapphire or SiC substrates. This is due to the absence of a crystalline lattice template between the GaN and the amorphous SiO2 layer. The dependence of lateral growth behavior, the crystalline character and the defect density of the overgrown GaN layers on growth conditions will be presented.
3:50 pm, Student Paper
Properties of InGaN Double Heterostructures and Quantum Wells Grown by Metalorganic Chemical Vapor Deposition: P.A. Grudowski, C.J. Eiting, J. Park, B.S. Shelton, D.J.H. Lambert and R.D. Dupuis, Microelectronics Research Center, University of Texas at Austin, Austin, TX 78712-1100
High-quality InGaN/GaN epitaxial films and heterostructures are of great importance for a wide variety of electronic and optoelectronic devices. In this talk, data are presented on the growth of InxGa1-xN/GaN and InxGa1-xN/InyGa1-yN heterostructures and quantum wells by low-pressure (Ptot=76-100 Torr) metalorganic chemical vapor deposition (MOCVD). The films are grown on sapphire substrates using trimethylgallium, triethlgallium, trimethylindium, and ammonia with both H2 and N2 carrier gases. Double-heterostructure GaN/InGaN/GaN films are grown employing a variety of In/[In+Ga] molar flow ratios, V/III flow ratios, temperatures, growth rates, and ammonia sources. The InGaN growth rate and alloy composition are found to depend upon the growth temperature and the In incorporation is strongly dependent upon growth kinetics. The films have been characterized by room-temperature (300K) and low-temperature (4.2K) photoluminescence (PL), cathodoluminescence (CL), X-ray diffraction, secondary-ion mass spectrometry, and transmission electron microscopy. Room-temperature PL spectra of single InGaN films and double heterostructures show relatively narrow linewidths with the narrowest PL (for a given alloy composition) measured for the films grown at the higher temperatures (e.g. =396.5nm, FWHM=15.3nm). The 300K PL spectra from 10-period InGaN/InGaN MQW structures (5 nm In0.15Ga0.85N wells, 10 nm In0.05Ga0.95N barriers) grown at ~760°C exhibit intense 435 nm emission with a FWHM of ~45 nm. Five period InGaN/GaN MQW structures (10 nm In0.15Ga0.85N wells and 10 nm GaN barriers) grown at 810°C show bright ~430 nm 300K PL emission with linewidths of ~35 nm. Narrow 4.2K PL spectra for the bulk InGaN layers (FWHM=5.8nm for x=0.11) and the MQW heterostructures and 300K CL data revealing spatially uniform luminescence from the single layers and QW structures will also be presented. *Work supported in part by DARPA, Ford Motor Co., NSF, ONR and the State of Texas.
Incorporation and Desorption Kinetics of Ga on GaN(0001) Grown by Gas Source: J.R. Jenny, J.E. Van Nostrand and R. Kaspi, Wright Laboratory (WL/AADP), Wright-Patterson Air Force Base, OH 45433-7323
The incorporation kinetics of gallium during GaN(0001) and AlGaN(0001) growth by gas source molecular beam epitaxy on c-plane sapphire substrates are investigated. Desorption kinetics of gallium are studied with desorption mass spectrometry (DMS). This technique allows for the determination of a growth phase diagram exhibiting three regimes including: a) gallium limited growth, b) nitrogen limited growth, and c) growth with Ga accumulation. These growth maps were developed as a function of growth conditions (substrate temperature, surface gallium coverage, and ammonia flux). First order and zeroth-order kinetics were observed for the total desorbing flux from coexisting surface phases. Activation energies and frequency factors were extracted from the Ga desorption measurements using a model based on first-order desorption kinetics. Incorporation of gallium and formation of gallium pooling is found to exhibit a strong dependence on substrate temperature. For example, the minimum ammonia required to incorporate all incident Ga (J(Ga)=0.1 ML/s) is reduced by a factor of two when the temperature is increased from 725 to 750°C. Electrical and optical properties of epitaxial GaN films as a function of the proximity to the growth phase boundaries will be presented.
Molecular Beam Epitaxy of GaN: Incorporation and Desorption of Volatile Species: S. Guha, N.A. Bojarczuk, F. Cardone, D.W. Kisker, IBM T.J. Watson Research Center, PO Box 218, Yorktown Heights, NY 10598
Of the elements used typically for doped GaN and InGaN growth by molecular beam epitaxy (MBE), Ga, In, N, Mg and Si, only Si is "well behaved" in terms of incorporation behavior during growth, rendering MBE of GaN quite complicated. In an attempt to understand the growth behavior of GaN, we have carried out a study of the incorporation behavior of these volatile species and their effect on the film properties. Mass spectrometry based measurements of mean surface residence lifetimes for Ga and In on GaN(0001) yield a desorption activation energy of 2.2 eV for Ga adatoms and a surface lifetime of 1-5 seconds in the temperature range of 680-750°C. Indium shows a higher temperature (>620°C) weakly bonded adatom phase, suggesting difficulty in In incorporation at temperatures beyond this value. Extensive SIMS measurements on Mg doped films indicate firstly that the incorporation ratio of Mg in the temperature range typical for GaN growth is <10-3. Secondly and more importantly, the measurements show that at a fixed substrate temperature the incorporation appears to be invariant to the Mg arrival rate, but on the other hand increases as the substrate temperature is decreased. This indicates that a simple model for evaporant incorporation during MBE is not applicable for Mg incorporation and we discuss possible mechanisms. Finally we argue that the high temperature limits to GaN growth is controlled by surface evaporation due to the vacuum environment in MBE, which is not surprising in itself: but we show that it is not uniform, but non-uniform surface evaporation that poses the limitation and results in microstructural degradation.
Gas Source MBE of GaN on (111) and (001) SIMOX Substrates Using Hydrazine: V.G. Antipov, A.I. Guriev, V.A. Elyukhin, R.N. Kyutt, A.B. Smirnow, N.N. Faleev, A.F. Ioffe Physico-Technical Institute, 26 Polytekhnicheskaya, St. Petersburg 194021, Russia; S.A. Nikishin, G.A. Seregin, H. Temkin, Electrical Engineering Department, Texas Tech University, Lubbock, TX 79409
Growth of GaN on compliant substrates offers a possibility of significant defect reduction. In addition, for compliant substrates related to Si, there is a technologically interesting possibility of integrating GaN and Si devices. We report on the growth of single-crystal GaN on (111) and (001) oriented commercial SIMOX (Si-SiO2-Si) substrates by gas source MBE with hydrazine as a nitrogen source. The SIMOX substrates consisted of either 200 nm thick or 2 µm thick layers of Si, with the surface orientation of (111) and (001), respectively, formed on top of buried oxide. Immediately prior to growth the substrates were outgassed at 1000°C. Clean surfaces were obtained by this procedure, as judged by RHEED and LEED observations of the 7x7 reconstruction pattern. Thin (20/40nm) layer of GaAs was deposited first on the silicon surface and then nitrided, under a flux of hydrazine, before commencing the growth of GaN at a substrate temperature Ts=550-600°C. Expitaxial layers of GaN, ~0.5µm thick, were grown at a growth rate of 400-600Å/hr and with V/III ratios in the range of 100/500. The structural studies by RHEED, LEED and XRD showed single-crystal structure of GaN epitaxial layers. The XRD analysis also showed single phase cubic GaN on SIMOX(001) and the presence of a cubic phase in hexagonal GaN/SIMOX(111), expected at low growth temperature. The structural quality of GaN films was evaluated by x-ray measurements in the w-scanning mode; the FWHM ranged from 75 arcmin to 90 arcmin. CL spectra of layers grown on (111) substrates show strong emission in the UV region (360/380 nm). An increase in the N2H4/Ga flux ratio, at a constant Ts, resulted in red shift of the emission maximum, consistent with decreased hexagonal GaN content.
CHAIR: Laura Wills, Hewlett Packard Laboratories, 26M, 3500 Deer Creek Road, Palo Alto, CA 94304
CO-CHAIR: Tim Sands, Department of Materials Science and Mineral Engineering, University of California, Berkeley, Berkeley, CA 94720-1760
1:30 pm, Invited
Ferroelectric Thin Films and Device Integration: C.A.P. Araujo
Ferroelectric thin films prepared from metallorganic precursors have found applications in semiconductor devices in the last few years. This paper reviews our experience in Ba1-xSrxTiO3 and layerd perovskites such as SrBi2(NbTa)2O9 in devices such as GaAs MMIC's for PHS mobile phone circuits and non-volatile memory in smart cards and embedded microcontrollers. The survey includes material synthesis, advanced deposition techniques, device physics and characterization.
2:10 pm, Invited
Electronic Fatigue in Perovskite Ferroelectrics: W.L. Warren, D. Dimos, G.E. Pike and B.A. Tuttle, Sandia National Laboratories, Advanced Materials Lab, MS 1349, 1001 University Blvd., Albuquerque, NM 87185-1349; H.N. Al-Shareef, Micron Technology Inc., Boise, ID 83707-0006
Since the readout process in ferroelectric (FE) nonvolatile memories can switch the polarization state of the FE, it is important to understand any possible degradation processes that may occur over many write/read pulses, or polarization reversals. Many models have been proposed to explain polarization suppression in FE materials. Some models include: electronic charge trapping at domain walls, and charged ionic defect sites such as oxygen vacancies (VO) pinning domain walls. It is impossible to distinguish between these effects from purely electrical measurements since they globally lead to a suppression in the amount of switched polarization; however, significant insight has been provided through studies of different electrode materials and photo-induced fatigue and restoration. We show that the electronic charge trapping is key to understanding the fatigue process. This is shown in that a loss of switchable polarization could be induced in PZT thin film, bulk ceramic and single crystal capacitors, by illuminating them with band-gap light, which excites electron hole pairs, while applying a dc bias just below the switching threshold. Furthermore, we find that the switchable polarization of both optically-suppressed and electrically fatigued Pt/PZT/Pt capacitors can be essentially restored to its initial value by poling the capacitor while illuminating boundaries is a primary fatigue mechanism. As for the optical restoration, it is envisaged that the photo-excited carriers recombine with the trapped charge while the dc bias reorients the previously locked domains. In addition, we will show that nominally fatigue-free LSCO/PZT/LSCO and Pt/SrBi2Ta2O9/Pt capacitors can be made to exhibit significant polarization fatigue when illuminated with UV light during fatugue testing. These results demonstrate that both systems are susceptible to fatigue effects (i.e., domain pinning by electronic charge trapping), even though neither exhibits fatigue under "standard" test conditions (cycling to saturation/no light). In addition, capacitors that have been fatigued under illumination can be fully rejuvenated by applying a dc saturation bias with light or by electric field cycling without light, which indicates a field assisted recovery mechanism. These results suggest that fatigue, or the lack thereof, can be viewed as a competition between domain wall pinning and unpinning. More importantly, this shows that the oxide electrodes do not eliminate the electronic charge trapping phenomenon in the PZT thin films: it simply appears as though the electronic charge traps are simply less stable using oxide electrodes.
Growth and Ferroelectricity of Epitaxial BST/SRO Capacitors on Si using Epitaxial (Ti,Al)N Barrier Metal: K. Sano, K. Abe, S. Komatsu, N. Yanase and T. Kawakubo, Materials and Devices Research Labs, R&D Center, TOSHIBA Corporation 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki 210, Japan
Epitaxial (Ba,Sr)TiO3 (BST)/SrRuO3(SRO) capacitor cell is quite promising not only for giga-bit level DRAM integration, but also for ultrahigh density ferroelectric memory . The key point of the epitaxial capacitor cell using oxide dielectric oxide bottom electrode on Si is the epitaxial barrier metal, which has a high oxidation resistance. We have developed epitaxial (Ti,Al)N barrier metal for the first time, thus the epitaxial capacitor cell can be realized. Epitaxial (Ti,Al)N films were grown on Si (100) by the low enerygy reactive ion beam deposition (R-IBD) method. The epitaxial relationship was confirmed to be (Ti,Al)N (100)//Si (100), (Ti,Al)N <110>//Si <110> using XRD, RHEED, and TEM. Epitaxial BST/SRO capcitors were grown by rf-magnetron sputtering at the substrate temperature of 600oC in Ar/O2. Oxidation test of bare (Ti,Al)N films were carried out in flowing pure O2 at different temperatures above 600oC, and oxidized layer thickness was elvaluated by AES. The most important results which we have obtained in this work are as follows: (1) Epitaxial (Ti,Al)N(100) was grown on Si (100) substrate by R-IBD at 600oC. (ii) (TiAl)N showed an excellent oxidation resitance above 600oC in a pure oxygen environment. The oxidation rate of TiN decreases by more than one order of magnitude by adding AlN, and decreases by a factor of four due to epitaxial growth. (III) The epitaxial capacitor cell, BST(100)/SRO(100)/Pt(100)/TiAlN (100) on Si (100) was successfully obtained and showed strong ferroelectric properties. The c-axis of BST was elongated due to mismatch of these lattice parameters. The epitaxial BST/SRO capacitor on Si using (Ti,Al)N barrier metal has submicron process compatibility, and is obviously one of the most attractive candidates for deep submicron ultrahigh density memories.
3:10 pm, Break
3:30 pm, Invited
Charge Transport and Dielectric Behavior of (Ba,Sr)TiO3 Thin Films Deposited by Liquid-Source MOCVD: S.K. Streiffer, C. Basceri, C.B. Parker, S.E. Lash, W.J. Lee, and A.I. Kingon, Department of Materials Science and Engineering, North Carolina State University, Raleigh, NC 27695-7907; S. Bilodeau, R. Carl, and P.C. Van Buskirk, Advanced Technology Materials Inc., 7 Commerce Drive, Danbury, CT 06804; S.R. Summerfelt, Texas Instruments, M/S 147, PO Box 655936, Dallas, TX 75265
(Ba,Sr)TiO3 (BST) is a leading candidate for use as the high-permittivity dielectric in a variety of advanced IC applications, including ultra-high density dynamic random access memories and bypass and decoupling capacitors. Although BST films have been extensively investigated by many groups, a comprehensive understanding of the dielectric and electrical properties that are relevant for these applications has not been fully established. Of particular concern, relatively few microstructure-properties relationships have been unambiguously determined for BST films deposited by MOCVD, even in cases where satisfactory empirical descriptions of a given response exist. In this contribution, we will present a summary of our work on the dielectric and electrical behavior of BST thin films deposited onto Pt/SiO2/Si by liquid-source MOCVD, with Pt, Ru, and Ir top electrodes. Emphasis will be placed on understanding the impact of film microstructure and electrode material on three areas: (1) the capacitance-voltage response, (2) the true leakage current, and (3) degradation/failure mechanisms. The interrelationships between these three areas will be outlined, particularly with regard to how changes in defect distribution across a film lead to changes in the true leakage and in the capacitance-voltage behavior.
Charge Dissipation due to Dielectric Relaxation Currents in Barium Strontium Titanate Capacitors: S. Zafar, R.E. Jones, B. Jiang, P. Zurcher, D.J. Taylor, B.E. White, P. Chu, B. Melnick and S. Gillespie, Materials Research and Strategic Technologies, Motorola, 3501 Ed Bluestein Boulevard, Austin, TX 78721
In recent years there has been an increasing interest in high dielectric materials such as barium strontium titanate (BST) for dynamic random access memory (DRAM) capacitors. The fundamental materials requirements for the storage capacitor dielectric are high charge storage density and low charge dissipation. This presentation will focus on the charge dissipation due to dielectric relaxation currents in thin film BST capacitors. Dielectric relaxation current is an important cause of charge dissipation and therefore needs to be carefully monitored. The conventional method for measuring dielectric relaxation current is to measure current as a function of time. Since the dielectric relaxation current decreases with time, it is essential to measure currents at short times (1µsec to 1 sec). the accurate measurement of currents at short times is difficult and requires elaborate experimental setup. An alternate method for extracting relaxation currents from capacitance versus frequency data is presented. This method uses fourier transformation to convert the data from the frequency domain to time domain. The present method is fast and robust in comparison to current measurements. The accuracy of this method is verified by comparing data from current measurements with those from capacitance measurements. Using this method, the charge dissipation due to dielectric relaxation in BST films deposited by different processes such as spin-on, sputtered and metal organic chemical vapor (MOCVD) is compared.
4:30 pm, Late News
4:50 pm, Late News
CHAIR: Umesh Mishra, University of California, Electrical Engineering Dept., Santa Barbara, CA 93106
CO-CHAIR: Eric S. Harmon, Mellwood Laboratories, Inc, 1291 Cumberland Avenue, Suite E, West Lafayette, In 47906
1:30 pm, Student Paper
Study of Low-Temperature Grown GaAs Cap Layers in Device Application: V.R. Kolagunta, H.J. Ueng, D.B. Janes, K.J. Webb, D.I. McIntruff, M.R. Melloch and J.M. Woodall, School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907
Low-temperature grown GaAs (LTG:GaAs) has generated a lot of interest because of low carrier lifetimes and its possible applications in fast optical devices. The minority carrier lifetime also prevents the oxidation in ambient of the LTG:GaAs material and is effective as a cap/passivation layer. High quality non-alloyed ohmic contacts to n+ GaAs with contact resistance of 2-5 x 10-7 cm2 have been fabricated using thin (20 - 100 Å) LTG:GaAs cap layers on n++ (1x1020 doped) GaAs layers. Recent scanning tunneling microscopy and XPS studies of the surface indicate that LTG:GaAs is stable upon air exposure and that the layer oxidizes more slowly and to a lower terminal thickness than stoichiometric GaAs. This makes LTG:GaAs cap layers viable for ex-situ device processing. In this paper we shall demonstrate the potential of exploiting the chemical and electrical properties of thin LTG:GaAs cap layers in device fabrication. The study involves controlled etching of the thin LTG:GaAs cap layer using various techniques to modify the electrical properties of the surface. We have made Ti/Au non-alloyed ohmic contacts using a 35Å LTG:GaAs cap layer to 100 Å thin n++ (1x1020 doped) GaAs layer grown on semi-insulating substrates with contact resistances of 1-1.5x10-6 cm2. TLM patterns fabricated on the above contact layer were then used to monitor its stability under various oxidizing ambients. Chemical oxidation using a hydrogen peroxide ambient and photo-oxidation induced by exposure to UV light under water were used to study the stability of the cap layer. Anamolous behavior including increased etching of the LTG:GaAs cap near the metal contact pads indicated by increasing pad to pad resistance with decreasing pad separation has been observed. Controlled etching of the top-contact layer before metalization allows modification of the GaAs surface properties including conversion of the nature of the contacts from ohmic to Schottky. A complete non-alloyed MESFET process has been developed using modification of the 35Å LTG:GaAs cap layer and using identical Ti/Au metalization to provide both the ohmic Source-Drain contacts and the Schottky gate contacts. Modification of this process to include a self-aligned T-gate is in progress and shall also be presented. The LTG:GaAs cap layer has also been effectively used to provide low top-contact resistance in vertical resonant tunneling diodes fabricated on a semi-insulating substrate wherein the contact to the bottom n+ layer is achieved by a self-aligned Au-Ge-Ni alloyed contact. The non-alloyed top-contact structure thus allows one to achieve the low-resistances necessary for such devices while allowing implementation of devices with quantum structures as close as a few hundred Angstroms from the top surface. The stability of the top-contact layer structure under the anneal conditions required to activate the bottom alloyed contacts shall also be discussed.
Space-Charge Controlled Conduction in Low-Temperature Grown Molecular-Beam Epitaxial GaAs: P. Kordos, M. Marso and A. Förster, Institute of Thin Film and Ion Technology, Research Centre Jülich, D-52425 Jülich, Germany; J. DFarmo, Institute of Electrical Engineering, Slovak Academy of Sciences, SK-84239 Bratislava, Slovakia
Behavior of low-temperature (LT) molecular-beam epitaxial GaAs in a broad range of applied electric fields needs to be known for better understanding the physics of this material as well as the optimization rules of devices with LT GaAs. However, on this topic only few results have been reported yet. Current transport in LT GaAs of different thicknesses grown at 200-400°C on n+-GaAs substrates is studied by means of current-voltage-temperature (J-V-T) characteristics. Space-charge effects are taken into account and modeling of J-V-T characteristics is performed. Obtained results can be described as follows: i) Experimental J-V-T characteristics at intermediate fields (i.e. between low-field ohmic and high-field pre-breakdown regions) exhibit a sublinear J~Vx dependence (x<1) followed by a superlinear Mott-Gurney behavior (x2-3). The sublinear and superlinear regions can be observed depending on the growth, annealing and measurement temperatures, as well as on the thickness of LT GaAs. ii) The average electric field of a sublinear onset, attributed before to the electron velocity saturation, is irreversible proportional to the LT GaAs thickness and in particular samples can be observed far below 1 kV/cm. Considering space-charge effects in the vicinity of the LT GaAs junction (contact and near contact), a highly inhomogeneous field distribution exists across the thickness (field profiles calculated for structure with different parameters will be shown). Therefore, current saturation effects need to be interpreted with caution. iii) Another evidence of the junction space-charge effects on the LTR GaAs conduction follows from the low-field resistivity vs thickness data for samples under study. Much higher resistivities (e.g. p6x108 cm for 0.5µm thick sample grown at 200°C) than known from van der Pauw measurements are obtained. It was reported before that high resistivity results from a lack of hopping due to the n+-contact used. However, the resistivity decreases with the thickness and the rxd-product is kept near constant, similarly as known for trap rich SI GaAs. iv) The apparent activation energy of deep traps, resulting from Arrhenius plot of the low-field resistivity, decreases with increasing the thickness (e.g. 0.76, 0.70 and 0.64 eV for 0.5, 2 and 4 µm respectively). The junction effects play less significant role in thicker samples, thus smaller activation energy seems to be more correct. So better agreement comparing to values reported on planar LT GaAs samples (0.67 eV) is obtained. v) The sublinear region is observed independently on the LT GaAs thickness (however in very thin samples the pre-breakdown region can cover the sublinear one) and is more pronounced if hopping is less contributing to the conduction, i.e. at higher growth or measurement temperatures. The superlinear region, which exists at higher average fields than sublinear ones, is observed if hopping is considerable contributing to the conductance, i.e. at lower growth, annealing and measurement temperatures. Detailed study of these effects is in progress. In conclusion, it is shown that space-charge effects at the LT GaAs junction needs to be considered at the analysis of LT GaAs properties. On the other hand, J-V-T measurements at intermediate fields can be used as a characterization method of LT GaAs behaviour.
2:10 pm, Student Paper
Investigation of Electrical Properties of Low Temperature GaAs and Al0.3Ga0.7As Metal-Insulator-Semiconductor Diodes: R.V.V.V.J. Rao, T.C. Chong, W.S. Lau, L.S. Tan and N. Lim, Department of Electrical Engineering, National University of Singapore, 10 Kent Ridge Crescent, Singapore 119260
Defects formed at the interface between low temperature (Al,Ga)As gate layer and n-GaAs channel layer during the in-situ annealing of the low temperature (Al,Ga)As layer can significantly affect the performance of Metal-Insulator-Semiconductor Field Effect Transistors (MISFETs) at RF frequencies. Studies were carried out on MIN diodes to evaluate the interfacial quality of the low temperature layer and n+-GaAs layer. In this work, we present the electrical characteristics of LT-GaAs and LT-Al0.3Ga0.7As MIN diodes, with and without an AlAs barrier layer between the LT-(Al,Ga)As and n+-GaAs layers. The low temperature layers were grown at 280°C by Molecular Beam Epitaxy (MBE). The resistivity of 2µm LT-GaAs layer was found to be 107 ohm-cm with a breakdown voltage of 20V while those of 2µm LT-Al0.3Ga0.7As layers are 1010 ohm-cm and 47V respectively. Transient Current Spectroscopy (TCS) studies revealed high concentration of defect states in the transitional region of the LT-GaAs and the n+-GaAs layers, and a dominant electron trap with an activation energy of 0.52eV. On the other hand, in LT-Al0.3Ga0.7As, a shallow trap at 0.36eV and two deep level traps at 0.85 eV and 1.12 eV were observed. For the LT-Al0.3Ga0.7As with AlAs barrier layer, only the trap at 1.12eV was observed. This suggests that the traps at 0.36eV and 0.85eV are likely due to defects arising from the out-diffusion of excess As from the LT-Al0.3Ga0.7As to the n+-GaAs during annealing. Frequency dispersion studies showed improvement of LT-GaAs samples with AlAs barrier layer over those without AlAs barrier layer. We observed similar results for LT-Al0.3Ga0.7As with and without AlAs barrier layer. However, LT-Al0.3Ga0.7As MIN diodes displayed less frequency dispersion as compared with LT-GaAs MIN diodes. The above results indicate that LT-Al0.3Ga0.7As with AlAs barrier layer is a good candidate for the gate insulator of MISFET devices.
Effects of Low Temperature GaAs on Dry-Etch Damage in AlGaAs/GaAs High Electron Mobility Transistor Structures: C.-H. Chen, J.P. Ibbetson, E.L. Hu and U.K. Mishra, Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106
Through ion channeling and rapid defect diffusion, relatively low energy ions (~300 eV) can produce deeply penetrating damage profiles, extending more than 100nm into the substrate during ion-assisted etching processes. For electronic devices, this can result carrier depletion or degraded carrier mobility. Using multiple quantum well (MQW) probes, we had previously demonstrated that a thin layer of annealed GaAs (~210Å) grown at low temperature (LT-GaAs) can efficiently reduce the observed ion-induced defects; the improvement appears to have a correlation with the microstructure of the LT-GaAs, and is particularly notable for samples annealed at 600°C. In this work, we have extended our studies on the effect of the LT-GaAs (~200Å) in mitigating ion damage in AlGaAs/GaAs high electron mobility transistor (HEMT) structures. A two-dimensional electron gas, formed by doping with Si, was grown on top of a MQW structure and capped by a thin layer of LT-GaAs (~200Å) grown at 250°C. This formed the 'HEMT' structures. Control samples were also grown, similar to the test samples in every way except for the formation of the capping layer of GaAs, grown at 600°C, rather than at low temperature. The combination of the MQW probes with the 2DEG allows us to characterize ion-induced changes in both the optical and electronic properties of the material. LT-GaAs capped samples were annealed at 600°C for 30s, and then Indium contacts were deposited and annealed at 350°C for 30s prior to ion bombardment. All samples were then exposed to the Ar+ ion beam for 3 minutes at beam energies of 350, 450, 550 and 600eV with an ion beam current of 50µA/cm2. The Hall measurements were carried out at room temperature and the photoluminescence (PL) measurements were performed at 1.4 K with argon laser excitation. The degradation in the carrier concentration and mobility due to ion-induced damage increases with increased argon ion energy, but a dramatic improvement in the damage profile results the inclusion of LT-GaAs, compared to "normal" GaAs capped samples. The improvement in photoluminescence taken from the 2DEG at low temperature follows the same trends as the electrical measurements. Preliminary results indicate that the presence of As precipitates in the LT-GaAs can effectively block ion-induced defects to damage the 2DEG regardless of the doping type of materials underneath and suggest the applications of LT-GaAs in improving the degradation of device performance resulted form the ion-assisted etching processes.
Effect of Growth and Anneal Conditions of Epitaxial Non-Stoichiometric Passivation on the Properties of GaAs FETs: N.X. Nguyen, Hughes Research Laboratories, Malibu, CA 90265; P. Chavarkar, J.P. Ibbetson, D. Grider and U.K. Mishra, University of California at Santa Barbara, Santa Barbara, CA 93106
Device application of Non-Stoichiometric (NS) materials, in particular LTG-GaAs and LTG-AlGaAs, as surface passivation layer in field effect transistors (FET) had been successfully demonstrated. The LTG material passivation has resulted in dramatic improvement in the breakdown voltage, hence power performance, of the devices. However, the question of the impact of the growth and annealing conditions of epitaxial non-stoichiometric passivation on the properties of GaAs FETs has not been addressed. Recently, we have devised an experiment that would effectively answer the above question. FETs with identical epitaxial channels had been fabricated with NS-epitaxial layers grown at different temperatures. These FETs had then been subsequently annealed at various temperatures and the properties of the FETs monitored to fully map the space of growth temperature and anneal conditions. In order to prevent the corruption of the ohmic and Schottky metals during the annealing of the NS-layer, refractory metals, which did not interact with GaAs, was used throughout the device. A schematic of the flow process is shown in figure 1. A nominal I-V characteristic of the device is shown in figure 2. The full channel currents of the various FETs were similar and therefore the comparison of the breakdown voltage is relevant. Figure 3 shows the breakdown voltages of the various FETs as a function of anneal temperature. Also shown is the variation of the breakdown voltage of the control sample, as a function of anneal temperature, where the epitaxial passivant was stoichiometric GaAs grown at 600°C. Breakdown voltage was defined as the voltage at with the gate-drain diode leakage was 1 mA/mm. The main feature of the breakdown voltage dependence on the preparation conditions of the NS passivant is the relatively monotonic decrease of the breakdown voltage with anneal temperature, independent of the growth temperature to a temperature of ~550°C. Then, in most samples, there is a precipitous drop in the breakdown voltage over a narrow range of temperature, down to the low breakdown voltage of the control sample. There are two possible reasons for this decrease. Either the concentration of the empty donors (equal to concentration to the filled acceptors assumed to be the Ga vacancy) reduces to below levels with are effective, or the spreading of the electric field due to the surface resistor formed by hopping condition is impeded. Details of these results along with a discussion will be presented at the conference.
3:10 pm, Break
3:30 pm, Student Paper
Removal Effect of Excess As and P Atoms in Low Temperature MBE with Atomic Hydrogen Irradiation: M. Yokozeki, H. Yonezu, T. Tsuji and N. Ohshima, Department of Electrical and Electronic Engineering, Toyohashi University of Technology 1-1 Hibarigaoka, Tempaku-cho, Toyohashi-shi, Aichi-ken, 441, Japan
The low temperature growth is required in MBE for forming an abrupt hetero-interface. However, excess group V atoms adsorb on a growing surface and the hetero-interface is disturbed in the heteroepitaxy with different group V atoms. Thus, it is essential to remove the excess group V atoms for growing the epitaxial layer with abrupt hetero-interface. This paper reports the removal effect of group V atoms by atomic hydrogen (H) irradiation in the epitaxy of GaAs and GaP. The effect was successfully applied to the low temperature growth of a (GaP)1(GaAs)3 strained-short period superlattice (SSPS) which requires the precise control of the deposition of group V atoms. In order to form a surface with excess As and P atoms, AS4 and P2 atoms were irradiated to GaAs(100) and GaP(100) surfaces at a low temperature of 350°C, respectively. RHEED patterns of the GaAs and GaP surfaces changed from the (2x4) to (2x2) and from the (2x4) to (3x2) patterns during the irradiation. Then, the atomic H was irradiated to the GaAs and GaP surfaces at 350°C, the RHEED patterns of GaAs and GaP surfaces recovered from the (2x2) to (2x4) and from the (3x2) to (2x4) patterns. In addition to the change of the RHEED patterns, it appeared in the XPS measurement that the amount of As and P atoms on the surfaces was reduced by atomic H irradiation. It was clarified from these results that the excess group V atoms can be removed by atomic H irradiation. The 300 nm-thick (GaP)1(GaAs)3 SSPS was grown by MBE on a GaP(100) substrate at the low temperature of 350°C under atomic H irradiation. The same structure was also grown without atomic H irradiation. The 2D growth was kept during the growth. Misfit dislocations with <011> orientations were observed at heterointerfaces of both samples by TEM. The <011> TED pattern of the (GaP)1(GaAs)3 SSPS layer grown under atomic H irradiation showed clear fractional spots caused by the fourfold-period type ordering superstructure. However, diffused fractional spots were observed in the TED pattern of the sample grown without atomic H irradiation. This means that the SSPS structure with an abrupt hetero-interface was formed by atomic H irradiation, while the hetero-interface was diffused in the sample without atomic H irradiation. The removal effect of excess As and P atoms by atomic H irradiation could lead to the growth of a high quality hetero-epilayer with less amount of point defects.
Analysis of V/III Incorporation in Non-Stoichiometric GaAs and InP Films Using SIMS: J.P. Ibbetson, U.K. Mishra, Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106; D. Doctor, T.Liu and D. Grider, Hughes Research Laboratories, 3011 Malibu Canyon Road, Malibu, CA 90265; Y. Gao, Charles Evans & Associates, 301 Chesapeake Drive, Redwood City, CA 94063
We have investigated the excess As content in GaAs films grown at low temperature (LT) by MBE using secondary ion mass spectroscopy (SIMS). Various films, 0.5-2 µm thick, were grown at different temperatures in the range of 350°C-225°C on GaAs substrates and left unannealed. The average As/Ga ratio measured by SIMS is larger in the LT layers compared to the stoichiometric buffer, increases with decreasing growth temperature, and correlates well with the lattice expansion of the LT epilayer determined by x-ray measurements. Moreover, the amount of excess As (up to ~2%) measured by SIMS agrees well with values in the literature obtained by other methods. SIMS depth profiles also consistently reveal that the As/Ga ratio in the LT layer is not uniform but decreases as the LT growth proceeds. In a 1 µm thick film, the amount of excess As typically decreases by ~50% from the peak value, and in some cases by as much as 80%. The largest peak As/Ga ratio observed thus far is 1.05, falling to 1.02 in the same layer over ~0.5 µm of growth. Applied to LT-InP grown on InP substrates (in a different MBE system), SIMS measurements reveal an astonishingly high average P/In ratio of 1.1 and 1.2 in films grown at 270°C and 220°C, respectively. TEM analysis reveals that the LT-InP layers are amorphous due to such a high P/In ratio. Nevertheless, a drop in the amount of excess P as the LT growth proceeds is also observed in these films, which suggests that the decreasing excess group V incorporation is quite general. One possible cause is a gradual rise in the substrate temperature during the growth of the LT layer, even though the temperature measured by the substrate heater thermocouple is constant. We plan to check this hypothesis by adjusting the thermocouple temperature during the LT growth to obtain uniform excess group V profiles. Our results show that SIMS is a useful technique for the evaluation of non-stoichiometric materials grown at low temperature, which, to our knowledge, has not been previously utilized in a systematic manner. Potentially, a complete data set of excess group V incorporation vs. growth temperature or V/III ratio can be extracted from a single growth run using SIMS. Measurement limitations to experiments along these lines will be discussed.
High Resolution X-ray Diffraction and Secondary Ion Mass Spectrometry Study of Low Temperature Grown GaAs: D.H. Tomich, K.G. Eyink, W.V. Lampert and J.S. Solomon, Materials Directorate, Wright Laboratory, Wright-Patterson AFB, OH 45433-6533; M.R. Mellochb, School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-1285
Low temperature growth of (non stoichiometric) NS-GaAs is finding considerable applications in device structures because of the unique properties of this material. These properties are attributed to the amount of excess arsenic in the film. In this study we utilize high resolution x-ray diffraction (HRXRD) and secondary ion mass spectrometry (SIMS) to analyze the amount of excess arsenic in the NS layers. The change in the (004) peak splitting with growth temperature was found to be similar to previous studies. However, by using the Pendelosüng structures associated with the NS-layers, lattice parameter changes were extracted for growth temperatures in the range of 270°C to 390°C. SIMS analysis of these layers was performed using a Cs ion beam. The CsGa+ and CsAs+ species were used to determine the excess arsenic concentrations. These species were chosen because of their relative insensitivity to matrix and chemical effects. Although oxygen was detected in the NS layers, no clear correlation was observed between growth temperature and level of oxygen detected. The arsenic concentration and distribution was determined only for the 270°C growth because of signal to noise limitations for films grown at the higher temperatures. The analysis of the 270°C growth because of signal to noise limitations for films grown at the higher temperatures. The analysis of the 270°C growth did show that the amount of excess arsenic was higher than the amount expected from the x-ray analysis. In addition, the excess arsenic concentration appeared constant throughout the layer and with an abrupt change at the NS GaAs/GaAs interface. Differences between the composition determined by SIMS and HRXRD will be discussed. The work at Purdue University was sponsored by AFOSR grant F49620-96-1-0234A.
4:30 pm, Late News
4:50 pm, Late News
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