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1997 TMS Annual Meeting: Thursday Session

DESIGN AND RELIABILITY OF SOLDERS AND SOLDER INTERCONNECTS: Session VII: Interconnect Design and Reliability in Electronic Packages III

Sponsored by: ASM-MSD Flow and Fracture; SMD Mechanical Metallurgy; EMPMD Electronics Packaging and Interconnection Materials Committees
Program Organizers: Dr. R.K. Mahidhara, Tessera Inc., 3099 Orchard Drive, San Jose, CA 95134; Dr. D.R. Frear, Sandia National Laboratory, Mail Stop 1411, Albuquerque, NM 87185; Professor S.M.L. Sastry, Washington University, Mechanical Engineering Dept., St. Louis, MO 63130; Professor K.L. Murty, North Carolina State University, Materials Science and Engineering Dept., Box 7909, Raleigh, NC 27695; Professor P.K. Liaw, University of Tennessee, Materials Science and Engineering Dept., Knoxville, TN 37996; Dr. W.L. Winterbottom, Reliability Consultant, 30106 Pipers Lane Court, Farmington Hill, MI 48331

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Room: 332

Session Chairperson: Dr. Zequn Mei, Hewlett-Packard Co., Electronic Assembly Development Center, 1501 Page Mill Road, Mail Stop 4U-3, Palo Alto, CA 94304; Professor K.M. Leung, Department of Physics and Materials Science, City University of Hong Kong, 83 Tat Chee Avenue, Kowloon, Kong Kong

8:30 am INVITED

QUALITY AND RELIABILITY OF BGA AND SMT COMPONENTS: Reza Ghaffarian, Jet Propulsion Laboratory, 4800 Oak Grove Drive, Pasadena, CA 91109

Spacecraft electronics including those at the Jet Propulsion Laboratory (JPL), demand production of highly reliable assemblies. JPL has recently completed an extensive study, funded by NASA's code Q, of the interplay between manufacturing defects and reliability of ball grid array (BGA) and surface mount electronic components. More than 400 test vehicles were assembled using ceramic and plastic BGAs, LCCs, J-leads, and gull wing components. These were subjected to thermal cycle testing and solder joint defects were logged prior to testing and solder damage propagation over time was documented. These findings offer valuable information to designers and quality assurance personnel alike on package robustness as well as in better understanding the defects that can actually lead to failure.

8:55 am INVITED

SOLDER JOINT RELIABILITY AND LIFE PREDICTIONS FOR VARIOUS SMALL OUTLINE PACKAGES MOUNTED ON FR-4 BOARDS: Suresh Golwalkar, Timothy Rothman, Paul Boysan and Robert Surratt, Intel Corporation, 1900 Prairie City Road, Folsom, CA 95630

TSOP or Thin Small Outline Packages have gained wide spread market acceptance throughout the electronic industry. This innovative and small footprint package was designed to fill a need created by the form factor specified for use in PCMCIA standard memory cards. However, with the broad and rapidly escalating acceptance of Flash products in the marketplace, this small outline package is being considered for a multitude of other use conditions. The small form factor of TSOP and accordingly short stiff lead form construction, requires further scrutiny in certain situations - specifically, applications requiring 20+ year lifetimes or others using 60 mil thick multi-layer FR-4 PCB's subject to extreme thermal cycling. Solder joint reliability is predominantly determined by two separate factors. The first being the surface mount process itself. Without a good initial solder joint, you can not expect good solder joint reliability. This fine pitch package (0.5 mm) requires different considerations than the existing 50 mil (1.27 mm) pitch type components. IR reflow profiles, solder volumes, and land pad layouts all contribute to proper fillet formation and a defect free solder joint. One must start with a good SMT process to have reliable solder joints. Second, is the use condition itself. Package/board configuration, operation conditions and thermal cycling of the board, drive solder joint reliability. In order to determine if TSOP is the correct package for a given application, various graphical presentations of failure rate versus service life are included in this paper. Solder joint evaluations were performed using various temperature cycle conditions. Data was taken using 64 mil thick FR-4 boards of various layer count and 20 mil thick 4 layer memory cards using 32Id, 40Id TSOP and 44Id PSOP packages. Temperature cycle conditions A, B and C were performed and Weibull probability plots were developed for each condition. Acceleration factors for solder joint fatigue is given by Norris and Landsburg equations. These include frequency transformations, temperature swing transforms, and a factor for variation of isothermal fatigue characteristics of solder joints between test and operating conditions. These equations yield use condition graphs. The graphs provided, show four different operational temperature swing conditions. Express, industrial, consumer, and computer conditions are depicted according to the IPC standards for these use variables. The extreme of the temperature swing and the frequency of swings per day, modulate the solder joint reliability. We have included both temp cycle condition A and B test data and modeled projections based on those. We feel that condition A more directly simulates real life use condition. Conditions B and C were used as highly accelerated conditions to obtain (trends only) swifter, but preliminary, failure predictions. As can be seen from temp cycle A cycling data, 50% failure point takes approximately six months to complete. PSOP data has ben included for completeness. As can be observed from the data, PSOP solder joint reliability, is oustanding for any application and any temperature range.

9:20 am INVITED

DEFORMATION ANALYSIS ON FLIP CHIP AND CSP SOLDER INTERCONNECT BY MICRODAC: D. Vogel1, J. Auersperg2, A. Schubert1, B. Michel1, H. Relchl1; 1Fraunhofer Institute for Reliability and Microintegration Berlin, Dept. Mechanical Reliability and Micro Materials, Gustav-Meyer-Allee 25, 13355 Berlin, Germany; 2Technical University Berlin, Forschungssohwerpunkt Technologien der Mikroperipherik, Gustav-Meyer-Allee 25, 13355 Berlin, Germany

In order to enhance thermo-mechanical life time of solder interconnects in flip chip and CSP assemblies the design of new products is optimized by the help of Finite Element (FE) simulations. Solder stress reduction is achieved selecting proper materials and assembly geometry. Life time estimations and trends can be obtained by fatigue models, e.g., a Coffin-Manson approach, utilizing calculated stress and strain distributions. The performance of FE modeling depends on the quality of the provided input data, i.e. on load conditions, geometrical layout, constitutive material laws and on material parameters. Lacking data necessarily leads to simplifications. Consequently, comparable strain and stress measurements are requested to make FE results reliable. Often Moire deformation measurements are utilized for microelectronics purposes to obtain data for comparison with FE findings. Unfortunately, the method is faced with difficulties, if very small structures like single bumps have to be investigated and resolved. The new microDAC method applied in this work can overcome these problems. The underlying measurement principle is a correlation based computer algorithm. It allows to track local object pattern during load. A set of local patter displacements is treated to get strain and shear fields over the object surface. Until now thermal and/or mechanical load on flip chip and CSP specimens is realized inside scanning electron microscopes, as well as for optical and laser scanning microscopes. The picked up images for different load states are processed by the microDAC computer code. Measurements have been accomplished for flip chip and chip scale package solder interconnects. E.G., strains inside eutectic PBSn bumps of flip chip assemblies with highly filled underfill material have been determined by microDAC. Bump stresses were caused by the thermal mismatch between a low cost FR-4 substrate and the silicon die, heating up the assembly from room temperature. Measured deformation fields have been compared with FE results. The main strain features of FE simulation and microDAC measurement results correspond with each other. The ìhardî underfill obstructs the shear of corner bumps. Consequently, shear strains (xy of corner bumps should not necessarily be a major reason of solder fatigue. Solder strains (xx in the perpendicular to the board direction are quite high. Their amount exceeds the value of unrestricted thermal strain of solder or underfiller material between a half and one order of magnitude. So, this strain component can significantly contribute to bump fatigue. Calculated (xx strains are at least three times lower than measured on the real component. The reason is assumed to be a anisotropic thermal expansion of the thin underfill layer. So, solder fatigue estimations only based on FE strain values can result in significantly higher life time values than realistic reached.

9:45 am INVITED

RELIABILITY FORMULATION FOR ELECTRONIC INTERCONNECTIONS: Eugene Atwood and Horatio Quintone, IBM Microelectronics, B/330-81A, Route 52, East Fishkill Facility, NY 12533

This paper describes a novel reliability methodology, supported by data, which includes a rigorously derived stochastic formulation. As an introduction to this topic, the paper reviews and critiques methods currently used in the field of electronic interconnection reliability and presents supporting data illustrating the arguments set forth. Plausible physical explanations are presented for each of the factors used in the IBM modified Coffin-Manson acceleration model. The acceleration model is challenged because of its form which assumes linearly independent factors. A review of the log normal and extreme value distributions, commonly used to model system reliability of electronic interconnects, highlights deficiencies and violations of some of the basic mathematical axioms i.e., "closure property". Additionally we present a refutation of "theoretical derivations" that have put forward to establish the validity of the log normal distribution as a model of fatigue fracture mechanisms. With regard to the main topic: today's thermal environments can no longer be defined by simple periodic functions, i.e., a fixed frequency and amplitude, but instead they tend to be "highly no-periodic" and of random nature. The randomness can be a result of the synergy between operating systems, software, use patterns and CMOS technology, e.g. temperature fluctuation patterns resulting from power management schemes defined in today's electronic devices. Present reliability formulations are not tailored to deal with this randomness. A rigorous formulation is presented that accounts for non-deterministic environments. The method treats the problem stochastically including the use of a novel distribution for time-to-fail, SCRIP (Statistics of Crack Initiation and Propagation) developed by the authors et al, and other system reliability formulations. An additional methodology is proposed which formulates electronic interconnection reliability in the presence of these random environments and extends the use of cycle/time based reliability assessments commonly used in the industry. The method consists of performing a series of renormalizations by discrete auto correlation and convolution integrals which are used to determine to determine the spectral power density function of the random environment.

10:10 am INVITED

SOME PHYSICS, KINETICS AND EMPERICAL RELATIONSHIPS RELATED TO FAILURE OF SOLDERED JOINTS: Barry Schlund, Reliability Engineering Department, M/S H2121, Motorola GSTG, 8201 E. McDowell Road, Scottsdale, AZ 85252

The primary purpose of this paper is to provide the physical reasons behind what appears to be many self-contradictions encountered in solder reliability testing and experience. This is accomplished by presenting the underlying physical aspects of solder reliability, including workmanship, metallic and intermetallic bonding, interface mechanisms, diffusion, vacancy and void formation, work-hardening and softening, as well as smooth versus chaotic stress-strain behavior. Also discussed, is the criterion for successful application of finite element analyses in fatigue life calculations. It is hoped that this work will help bridge the gap between practitioners with opposing beliefs, for example those who believe in chaotic stress-strain behavior versus those who believe in smooth behavior. General guidelines for estimating the appropriate input conditions in the absence of accurate life profiles are provided. The use of the tool is demonstrated with several examples. These include: Thin Outline packages, Quad Flat packs, J-leaded components, and leadless Chip Carriers. A comparison of observed failures and calculated times to failure is provided.

10:35 am BREAK

10:45 am INVITED

COMBINED HEAT TRANSFER AND THERMAL LOAD ANALYSIS FOR FATIGUE LIFE PREDICTION OF SOLDER JOINTS OF RESISTORS: Hasan U. Akay, A. Bilgic and N. H. Padyar, Department of Mechanical Engineering, Purdue School of Engineering and Technology, IUPUI, Indianapolis, IN 46202

Despite the studies performed in the last two decades to understand the fatigue behavior of the solder joints used in the electronic packages, the problem still draws big attention among the electronic package manufacturers. Fortunately, the studies performed provided a great improvement in the information about the behavior of the solder material under low-cycle-fatigue conditions. Based on the available information about the mechanical and fatigue behavior of solder material under thermal loads, the present authors developed the volume-weighted averaging technique for the fatigue life prediction of solder joints (A. Bilgic, "Fatigue Life Prediction Methods for Thermally Loaded Solder Joints Using the Finite Element Method", Master of Science Thesis, Purdue University, Indianapolis, IN) and H. U. Akay, N. H. Padyar and A. Bilgic, Fatigue Life Predictions for Thermally Loaded Solder Joints Using a Volume-Weighted Averaging Technique, ASME Journal of Electronic Packaging, 1996 (in Review). The method consists of calculating the stresses and strains generated within a specific package by use of the finite element method and then correlating the calculated stress-strain response to the fatigue life by use of an energy-based fatigue life prediction criterion. The method was used to predict the fatigue lives of several arbitrary solder joints and the predictions were compared with the experimental data. The predictions were very encouraging. It is stated that the method does not differentiate between leadless and leaded solder joints or the loading applied on the packages. In addition, the method is very mesh-insensitive, implying that the number of nodes and finite elements used in the mesh has no major effect on the predictions. In this study, we extend our method to the fatigue life prediction of three-dimensional solder joints of resistors. The heating is provided by the power loading applied on the resistor. The differential thermal expansions within an assembly causes the thermal strains and stresses, as in the case in chip carriers. The analysis is performed in two steps: 1) A heat transfer analysis is performed to determine the spatial variations of temperatures during a power loading cycle; 2) Thermal stress analysis is performed to determine the thermal stresses and strains developed during the structure. The stress-strain response against the applied power loading is then used to predict the fatigue life using the previously developed volume-weighted technique and the fatigue life prediction criterion. The predictions are compared with the experimental data provided by others.

11:10 am

MECHANICAL PROPERTIES OF SN-AG COMPOSITE SOLDER JOINTS CONTAINING COPPER-BASED INTERMETALLICS: S.L. Choi, J.L. McDougall, T.R. Bieler, K.N. Subramanian, Dept. of Materials Science and Mechanics, Michigan State University, East Lansing, MI 48824

11:30 am

RELIABILITY OF A CHIP SCALE PACKAGE: Steve Greathouse*, Rao K. Mahidhara**, Vern Solberg**, Joe Fjelstad**, Tom DiStefano**, *Intel Corp., CH6-315, 5000 W. Chandler Blvd., Chandler, AZ 85226; **Tessera Inc., 3099 Orchard Drive, San Jose, CA 95134

Post stress reliability for Chip Scale Packages and their interconnects has been lacking in the industry. An evaluation of the Tessera µBGA package through the solder screening process, reflow profile, and resultant reliability data is given. Reliability data is compared to industry standard goals for stress ing. Further discussion of solderability methods and solder ball integrity via ball shear is also given.

11:50 am

CRATERING IN 90:10 Pb:Sn CAST COLUMNS FOLLOWING SHEARING IN CAST COLUMN GRID ARRAY (CCGA) PACKAGES: M. Nemiroff1, K. Economy2, Y. P. Geng3, T. H. Hao4, 1Cadence Corp., 10850 Via Frontera, San Diego, CA 92128; 2UNISYS Corp., 10850 Via Frontera, San Diego, CA 92128; 3Institute for Mechanics and Materials, University of California, San Diego, CA 92093; 4China Textile University, Shanghai, China

Void-like features have been observed on sheared surfaces on 90:10 Pb:Sn columns in ceramic cast column grid array (CCGA) packages. The feature sizes are typically 3-5 mils across. These features are not voids. They are crater-like fractures caused by the shearing tool. Shearing with a heavy tool causes extensive cratering. Shearing the columns with a razor blade produces far fewer, if any, of these void-like features. These craters are a concern since they can be mistaken for voids which affect the reliability of CCGA devices. The surface of these features are devoid of large (greater than 2-3 micron) tin-rich regions normally in the bulk of the column. The tin-rich regions have lower toughness than the Pb-rich matrix in the two-phase 90:10 Pb:Sn cast column. Cratering can be explained as a mechanism where the shearing tool creates a crack that propagates around these tin-rich regions. Micromechanical models have been established to simulate crack propagation (a) through and (b) around the tin-rich area. The results show that the energy released for case (b) is less than that of case (a) even though case (b) has a longer crack path.

12:10 pm INVITED

EXPERIMENTL STUDIES OF SMT SOLDER JOINT RELIABILITY: K. M. Leung, Department of Physics and Materials Science, City University of Hong Kong, 83 Tat Chee Avenue, Kowloon, Kong Kong

SMT solder joints between ceramic chip carriers and printed circuit boards are found in general to suffer large thermal strains and stresses during device operation under repeated power cyclings. A comprehensive study of the thermomechanical behavior of SMT solder joints has been performed under power cycling using different techniques of optical interferometry. This paper will discuss the detailed analysis of these experimental measurements and its implication on fatigue life estimation of SMT solder joints. Other major experimental studies on solder joints reliability performed at the City University will be reviewed as well.


12:30 pm


A thin layer of 6.0 to 8.0 microinches (0.1 to 0.2 microns) of electroless palladium deposited directly on the copper surface of a printed wiring board has exhibited excellent solderability. This new surface offers a series of advantages over the traditional Hot Air Solder Leveling (HASL). It is flat, coplanar, which is a must for successful screen printing of fine featured devices. It is lead free and environmentally friendly. Other than being solderable it is also wire bondable and has applications as a viable surface finish for contact switching or compression contacts. Characteristics of palladium are discussed. Data of solder joint reliability is presented. The data includes an in depth EDX analysis of metallurgy of the interface between palladium coated copper pads and the solder forming the joint, under various accelerated aging conditions. The solder joint has been subjected to 2000 thermal cycles per IPC standard testing procedures. The results indicate no impairment in resistivity of solder joint integrity.

12:50 pm

RELIABILITY EVALUATION OF CHIP SCALE PACKAGES BY FEA AND MICRODAC: J. Auersperg1, D. Vogel2, J. Simon1, A. Schubert2, B. Michel2, 1Technical University Berlin, Forschungssohwerpunkt Technologien der Mikroperipherik, Gustav-Meyer-Allee 25, 13355 Berlin, Germany; 2Fraunhofer Institute for Reliability and Microintegration Berlin, Dept. Mechanical Reliability and Micro Materials, Gustav-Meyer-Allee 25, 13355 Berlin, Germany

Chip Scale Packaging is one of new hot topics in electronic packaging where Chip Scale Packages are defined by size, which should be nearly chip size. Different types of CSPís have been developed. They may be classified by the technological concept, e.g. waferlevel (including molding), flip chip with interposer (rigid, flex) and the well known (BA. The mechanical reliability mainly is determined by the packaging technology. The package design has to compensate stresses caused by the thermal mismathc between its components. Different CSPís approaches were analyzed by thermomechanical Finite Element Analysis simulating a thermal cycling process with respect to the complex mechanical behavior of the different materials used, e.g. the creep effect in solder joints, the temperature dependence of material parameters, the visco elastic behavior of underfill materials. The results will be discussed from the aspect of an estimation of the mechanical reliability. Several types of SCPís with a great variety of materials used are evaluated in such a way. The sensitivity of the related values to changes of material and geometrical parameters was used to enhance the thermo-mechanical life time. Experimental methods are applied to obtain accurate input data for the FEA. The comparison of the results from FEA with those obtained from microDAC strain measurement method helps to fit the model data utilized in numerical simulations for more realistic physical models and makes the FE results reliable. This work is part of a national CSP project with partners from German industry.

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