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Session Chairpersons: Puligandla Viswanatham, Texas Instruments Inc., Circuit Card Assemblies, 2501 South Highway 121, Mail Stop 3450, Lewisville, TX 75067; Walter L. Winterbottom, Reliability Consultant, 30106 Pipers Lane Court, Farmington Hill, MI 48331
2:00 pm INVITED
ISSUES AFFECTING RELIABILITY OF SURFACE MOUNT SOLDER JOINTS: Sung K. Kang, IBM Corp., T.J. Watson Research Center, Room 37-250, P.O. Box 218, Yorktown Heights, NY 10598
Surface mount technology (SMT) has been practiced as the principal soldering method for the assembly of printed circuit boards (PCB) last ten years. SMT packages connected by solder joints occupy more than two thirds of a PCB real estate. SMT packages consist of both conventional formats such as small outline package (SOP), small outline 'J' leads (SOJ), plastic leaded chip carriers (PLCC), or quad flatpack (QFP), and fairly new packages such as thin small outline package (TSOP), tape carrier package (TCP), chip-on-board (COB), ball grid array (BGA), and many more. In this talk, recent developments of SMT soldering technologies are briefly reviewed, followed by discussion of several technical issues affecting the reliability of SMT solder joints. The subject matters to be discussed include solder joint defects, microstructure, interfacial reactions, thermal fatigue, and Pb-free solders.
2:25 pm INVITED
RELIABILITY CONSIDERATIONS WHEN CHOOSING WATER SOLUBLE FLUX FOR ELECTRONIC ASSEMBLY: Laura Turbini, Georgia Institute of Technology, School of Materials Science and Engineering, 778 Atlantic Drive, Atlanta, GA 30332
There is a need for a fundamental understanding of the interaction of processing chemicals such as fusing fluids, soldering fluxes and cleaning agents with printed wiring board substrates. This need is driven by two factors: (1) the increased density of today's electronic products creates voltage gradients which are high enough to enhance degradation modes which are not important for less dense circuitry, and (2) the elimination of chlorofluocarbons (CFCs) and other ozone depleting cleaning agents due to their destructive effect on the stratospheric ozone layer has lead to a proliferation of new soldering fluxes and cleaning agents whose interactions with the printed wiring board (PWB) are not well characterized. Water soluble fluxes have been effectively used in high volume electronic manufacturing operations for a number of years. Their use has increased dramatically as they provided an opportunity to eliminate CFCs in the cleaning process. They provide excellent soldering with low defect levels and with a proper cleaning process can produce highly reliable electronic circuits. However, some water flux and fusing fluid formulations contain ingredients which can have deleterious effects on the reliability of a product under certain operating and use conditions. There is a failure mechanism known as conductive anodic filament formation (CAF) which has been observed in PWBs boards treated with certain water soluble fluxes. This failure mode involves a debonding of the epoxy-glass interface and the formation of a conductive filament which grows along this interface from anode to cathode. This paper will report on those chemicals which tend to enhance this failure mode and will make recommendations on assuring the reliability of electronic assemblies.
2:50 pm INVITED
INFLUENCE OF COMPONENT SOLDERABILITY ON RELIABILITY OF SOLDER JOINTS: Colin Lea, National Physical Laboratory, Teddington, Middlesex TW11 0LW, UK
The commonest mode of service failure of solder joints on circuit board electronics assemblies is low-cycle fatigue cracking from differential expansion during power-up and power-down of the equipment. The resistance of a solder joint interconnection to fatigue cracking is governed by both its microstructure and its geometry. In turn, these are both governed by the soldering process and the manner in which the molten solder wets and flows on the component metallisation; the component's solderability. Data will be presented, for surface mount assemblies, that relate component/circuit board solderability to solder fillet shape, and in turn to solder joint reliability. The best fillet geometry varies markedly between the many different styles and compositions of metallisation found on surface mounting components. Furthermore, the pass/fail criteria of solderability measurements are not necessarily related to the required solder fillet geometry for best reliability. Both infra-red reflow and wave soldering have been used, since the use of solderability on solder fillet shape may be quite different for the different manufacturing routes.
3:20 pm INVITED
SOLDERABILITY AND SURFACE MOUNT SOLDER JOINT SHAPE PREDICTION: D.J. Lewis1, M.R. Notis1, G.C. Munie2, D.M. Noctor3, 1Materials Science and Engineering Department, Lehigh University, 5 East Packer Avenue, Bethlehem, PA 18015; 2Lucent Technologies, Naperville, IL 60563; 3Lucent Technologies, Bell Laboratories, Room 22W-208eo, 555 Union Boulevard, Allentown, PA 18103
As a part of a program supported at AT&T Network Systems for continuous improvement in solderability, solderability modeling, and solderability specifications, an assembly trial was performed to determine the correlation of assembly yield to different combinations of solder volume, component coplanarity, component aging, and solder alloy. Through the use of wetting balance data and assembly yield statistics, soldering process charts correlating assembly yield to solder volume and coplanarity show that severe lead surface finish degradation would require (unmanufacturable) component coplanarities of less than 1 mil to maintain 100% assembly yield. The 132 I/O, 25 mil pitch, BQFPs were pre-conditioned using high temperature and humidity to degrade lead surface finish. Standard tin-lead solder and three commercially available lead-free solders were used to vary the solder wetting characteristics. To determine a process window for solderability, solder volume was varied by using two different stencil thicknesses, and coplanarity was measured to determine the effect of mechanical tolerance. Electrical continuity and visual inspection showed that assembly yield decreased with decreasing solder volume, poorer mechanical tolerance, and increased component aging time. Wetting balance data showed trends for aging conditions, but a correlation to coplanarity was not found. Contact angle results indicate that tin-lead had best wetting properties however this conflicts with assembly trial results where tin-lead had the higher failure level than the lead-free alloys. The goals of this project were: to further define a process window for solderability with tolerances for volume and coplanarity distributions; (2) to refine solderability specifications; and (3) to verify a computer model used to assess solder joint geometry and joint quality based on solder alloy and component lead properties. Assembly yield was examined based on different combinations of solder volume, component coplanarity, component aging, and solder alloy.
3:45 pm BREAK
3:55 pm INVITED
A SIMPLE DESIGN TOOL FOR EVALUATING LOW CYCLE SOLDER FATIGUE OF PACKAGE TO BOARD INTERCONNECTIONS: Ted Carper, Robert Von Mayr and Puligandla Viswanatham, Texas Instruments Inc., Circuit Card Assemblies, 2501 South Highway 121, Mail Stop 3450, Lewisville, TX 75067
Low cycle solder joint fatigue analysis is an important aspect of assessing the package to board solder interconnection performance of circuit card assemblies. A simple analysis tool that takes into account the significant environmental conditions for storage, operation, transportation, etc., and calculates the number of cycles to failure for a given set of input parameters is described. These parameters include coefficient of thermal expansion (CTE) of individual elements of the assembly structures, temperature, duration, number and frequency of cycles. Both leadless and leaded component configurations are included in the design of this tool. Lead stiffness for leaded components are calculated using equations published in the literature.
4:20 pm INVITED
QUALIFICATION OF BALL GRID ARRAY ASSEMBLIES FOR SPACE FLIGHT APPLICATIONS: Sharon Walton, Kirk Bonner, Electronic Packaging and Fabrication Section, Jet Propulsion Laboratory, California Institute of Technology, 4800 Oak Grove Drive, Pasadena, CA 91109
JPL, in a partnership with an industrial consortium, is engaged in the investigation of reliability and quality issues of Ball Grid Array Packages as they may be applied to space flight electronics. Performing tests to determine the solder joint reliability of assemblies using BGAs under temperature cycling is proving to be a real challenge for test engineers. It was recognized early in the program that a large number of the BGA solder joints would be under test simultaneously and that some sort of computer based assistance would be required to accurately track the failures and the time at which they occurred. JPL has been using the National Instrument LabVIEW software and SCXI hardware to set up our system. The data acquisition program, DAQ.VI, was written around LabVIEW, a graphics based operating system. The program controls the temperature chambers, gathers data from the interface cards, logs data, and provides operator interface. This system can monitor over 1500 channels for electrical continuity and 32 channels for temperature. This software/hardware system greatly simplifies the task of monitoring and tracking failures and the conditions when the failures occurred of a large number of solder joint channels through the automatic gathering and recording of the test results onto a personal computer data base.
SOLDER JOINT INTEGRITY IN TESSERA'S µBGA PACKAGE: Rao K. Mahidhara1 Vern Solberg, Tom DiStefano1 and Steve Greathouse2, 1Tessera Inc., 3099 Orchard Drive, San Jose, CA 95134; 2Intel Corp., CH6-315, 5000 W. Chandler Blvd., Chandler, AZ 85226
Chip-scale packages (CSP) are miniaturized IC packages that are being developed for applications ranging from memory chips to advanced high-performance processors. Adaptable to volume manufacturing, this type of package offers the performance and size advantages of a bare die, while conforming to the established infrastructure for electronic assembly. Tessera's µBGA belongs to this new family of CSP, wherein the need to underfill the device has been eliminated. The reliability of solder joints in Tessera's µBGA package is presented. Modeling studies on solder joint integrity have been conducted via finite element analysis (FEA) to predict stress and strain distributions at the solder ball-joint interfaces and potential failure points. The modeling work is complimented by studies involving ball shear testing and, intermetallic growth via optical/SEM/EDAX techniques following long time static annealing and temperature cycling. These reliability studies are suggestive that Tessera's µBGAs are robust packages.
MECHANICAL AND CREEP CHARACTERISTICS OF Sn-3.5Ag FOR SOLDER-JOINT RELIABILITY: Hong Yang*+, P. Deane*, P. Magill* and K.L. Murty+*, *Microelectronics Center of North Carolina, Research Triangle Park, NC 27709; +North Carolina State University, P.O. Box 7909, Raleigh, NC 27695
Constant-load creep and stress relaxation tests of Sn-3.5Ag solder alloy were performed at high homologous temperatures from 25°C to 180°C. Single lap shear tests were conducted on joined flip chip packages with 33X33 area array of Sn-3.5Ag solder bumps. Tensile creep tests were performed on bulk solder specimens. The steady-state strain-rates span 7 orders of magnitude ranging from 10-9 to 10-12 (1/s). The apparent activation energy of creep was found to be 0.57 ev. The stress exponent (n) in the power-law creep equation is found to be about 10 which is unusually high compared to that for many other metals. A constitutive equation relating stress, temperature and strain-rate for Sn-3.5Ag solder alloy was established. Low-temperature dislocation-climb deformation mechanism (with dislocation-pipe diffusion) is believed to be dominant in the medium-to-high stress region with power-law breakdown at very high stresses. Numerical simulations of a flip chip package were performed to characterize the failure modes. The effects of different design parameters were studied with regard to strain accumulation and stress distribution in the package under thermal cycles. Recommendations are made for design optimization. This work has been supported by the Microelectronic Center of North Carolina.
LEAD FINISH COMPARISON OF THREE LEAD FREE SOLDERS versus EUTECTIC SOLDER: Mark A. Kwoka, Dawn M. Foster, Harris Corporation, Semiconductor Sector, P.O. Box 883, Melbourne, FL 32902
The use of lead in electronics manufacture will probably be disallowed in the not too distant future. While data is currently being taken regarding the material properties of lead free solders, very little has been published regarding how the new lead free solders will respond to existing methods of solderability assessment. This study will provide an I.C. component lead finish comparision of three selected lead free solders with standard 63/37 Sn/Pb solder using wetting balance and "Dip and Look" solderability test techniques. In addition, an association between board level soldering performance, wetting balance and "Dip and Look" solderability test parameters of the lead free solders will be established.
INTERFACIAL REACTION BETWEEN PALLADIUM AND LEAD-TIN SOLDERS: G. Ghosh, Dept. of Materials Science and Engineering, Northwestern University, Evanston, IL 60208-3108
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