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Session Chairperson: Sung K. Kang, IBM Corp., T.J. Watson Research Center, Room 37-250, P.O. Box 218, Yorktown Heights, NY 10598; Professor Jorma Kivilahti, Helsinki University of Technology, Materials and Manufacturing in Electronics, Vuorimiehentie 2A, Fin-02150 Espoo, Finland
8:30 pm INVITED
FLIP CHIP SOLDER INTERCONNECTIONS--A RELIABILITY PERSPECTIVE: Karl Puttlitz, IBM Microelectronics, B/330-1AX44-173, GFKA, Rt. 52, Hopewell Junction, NY 12533
The solder ball flip chip or so-called C-4 connection was introduced by IBM nearly three decades ago as an alternative to manual wire bonding whose productivity and reliability were not acceptable at the time. A very large data base indicates that flip chips are the most reliable interconnection scheme in the industry since its inception. Moreover, the combination of C-4 mounted die and alumina multilayer ceramic (MLC) substrates provided the highest overall package reliability. This paper will discuss several key technical attributes such the joint controlled collapse feature, self-centering and throughput which is independent of die I/O count. Joint design, process, compositional and metallurgical factors will be discussed in the context of the very significant effect they have on reliability as well. Flip chip technology is flexible, having been successfully utilized with several generations of chip carriers. Important also is the ability to predict the thermal-mechanical (fatigue) behavior of C-4 joints. When attached to ceramic carriers, the failure rate of flip chip joints obey a distance-from-neutral point (DNP) dependence defined by the Coffin-Manson (C-M) relationship. Modifications to the C-M relationship necessary for this application will also be discussed. It will be shown that the technology is sufficiently extendible to satisfy the trends of smaller, lighter, faster, denser, etc. which are expected to continue in the future. New developments such as chip underfill and future trends including DCA and their reliability implications will also be discussed.
8:55 am INVITED
A NEW RELIABILITY ASPECT OF HIGH DENSITY INTERCONNECTIONS: Jorma Kivilahti, Helsinki University of Technology, Materials and Manufacturing in Electronics, Vuorimiehentie 2A, Fin-02150 Espoo, Finland
Increasing importance of portability in telecommunication and consumer electronics is activating the research and development work on reliable, cost-effective fine-pitch interconnections and substrate technology alternatives. However, high density interconnections may produce increasing difficulties, e.g. in paste printing, component alignment and acceptable residual levels. Moreover, increasing microjoint densities are related to decreasing solder joint volumes, and therefore, it is even more likely that the whole solder volume will take part in the reactions, for example, between a solder, Flip Chip (FC) bump and substrate metallisation. Similar consequences of the miniaturization are encountered in the bump-limiting metallurgy; the total volumes (or thicknesses) of the diffusion barriers and adhesion layers and the original filler, alike, can transform into the matrix of intermetallics, which due to their inherent brittleness make the microjoints mechanically too weak to withstand thermal stresses. Accordingly, for confirming adequate reliability of microjoints it is essential to have better understanding and control on metallurgical compatability of dissimilar materials being in contact with each other. In this communication results of metallurgical studies on various FC bump-solder-substrate metallization reactions are presented. As specific examples, the bump-solder-substrate interactions have been studied experimentally with Au- as well as with Ni-bumped test chips, which were reflow-soldered with the eutectic SnPbAg filler at 235°C for various times onto Au/Ni- and Cu-conductors on the FR-4 substrates. The electrical properties, structural integrity and evolution of microstructures (i.e., intermetallics, Pb-rich solution or eutectic structure) of reflow-soldered Flip Chip joints were examined in detail with the conventional tests and materials characterization methods. For studying the metallurgical compatibility and controlling the reaction kinetics between Au, Ni and eutectic SnPb and SnPbAg, the wedge-shaped diffusion couple experiments which more clearly illustrate the effect of solder layer thickness on the volume fraction of the intermetallics in the microjoints, were conducted using the RMA flux as well as a vacuum furnace. The thermodynamics of the AuSnPb, NiSnPb and CuSnPb systems were critically modeled and used for rationalizing the observed bump-solder-substrate reactions in the Flip Chip joints as well as in the diffusion couples. On the basis of metallurgical considerations a new Pb-free solution to this "small-volume-problem" is also addressed.
9:20 am INVITED
ELECTRONIC PACKAGING DESIGN FOR RELIABILITY: William L. Olson, Motorola Corporate Manufacturing Research Center, 1301 East Algonquin Avenue, Room 1014, Schaumburg, IL 60196
Consumer electronics products continue to increase rapidly in complexity while shrinking in size. This trend is driving development of a variety of new electronic packages that provide much higher interconnect density/in2 of PCB surface - without compromising the product's reliability or quality. This challenge has resulted in a proliferation of packaging alternatives including PBGA's, COB, micro-BGA, CSP and DCA. Selecting the most appropriate package for a given product requires careful engineering of the product's features, reliability and cost. My presentation will review the various semiconductor packaging approaches with an emphasis on design for high value and reliability. Results will be presented for a new multi-flip chip BGA package which provides excellent interconnect reliability for reasonable cost.
9:45 am INVITED
A STUDY ON THE SOLDER JOINT RELIABILITY OF THE OPTOELECTRONIC PACKAGING WITH FLIP-CHIP BONDING: Jong Tae Moon, G.J. Joo, M K. Song, K.E. Pyun, H.M. Park, Semiconductor Research Division, Electronics and Telecommunications Research Institute, 161 Kajonj-Dong, Yusong-Gu, Taejeon, 305-350, Korea
The optical transmitter and receiver modules were fabricated by applying flip chip bonding process. It was possible that the degree of alignment accuracy controlled below 1 µm by the force of solder self-alignment. To minimize parasitic capacitance and inductance induced from the solder joint, the reflowed solder ball on Si substrate was varied from 100 µm to 5 µm. The Pb-In, Pb-Sn, In-Sn and In-Ag alloys as the bonding materials were deposited above UBM on the Si substrate by using thermal evaporation method. During the reflowing process, the behavior of solder ball formation, and the intermetallic compounds between the UBM and solder composition were inspected with various heating rates and the use of flux. During the flip chip bonding process, the solder joint shape and the gap between Si substrate and optical devices were controlled by means of a various temperature profiles and bonding force. The solder joints reliability of the flip chip bonded optical submodules were evaluated by shear, thermal shock, and thermal cycling test. In the case of the thermal shock test, the range of temperature was from 25°C to the liquid N2. Thermal cycling numbers were 1000 cycles from -40°C to 120°C. These samples were analyzed by optical microscopy, SEM/EDS and TEM.
10:10 am INVITED
RELIABILITY CHALLENGES AND MODELING OF MINIATURIZED SOLDERED ASSEMBLIES: Jean-Paul Clech, EPSI Inc., P.O. Box 1522, Montclair, NJ 07042
Miniaturized electronic packages have emerged that bring about new reliability challenges and, in some cases, have revived the concerns of Leadless Chip Carriers (LCCCs) on organic substrates: 1) most of these packages are leadless; 2) their Coefficient of Thermal Expansion (CTE) is low because of the high silicon contents of shrinking or disappearing packages; 3) the assembled packages may have a low stand-off height (for miniaturization purposes); 4) typical assemblies are very fine-pitch with micro-solder joints having smaller load bearing or crack propagation areas than conventional surface mount assemblies. The above attributes may be detrimental to long term solder joint integrity and suggest that reliability be looked at carefully, more so than with conventional surface mount assemblies. This talk will present thermal stress and reliability models that can help tackle those problems and ensure that assembly reliability is built-in during the early stages of product design. Two examples of engineering models of miniaturized assemblies will be discussed that enable rapid assessment of the impact of package geometry and materials on assembly reliability. The first example is a model of flip-chip assemblies with underfill. The model quantifies the solder joint relief provided by the underfill layer and its effect on assembly stiffness. The mechanics of flip-chip with underfill are unique since they involve an increase in assembly stiffness to provide for solder joint strain relief. The analysis is that of a multilayer structure (board/underfill/die) that deforms under thermal loads and 'external' forces and moments exerted by the solder joints. Predicted shear strains in the underfill layer are in good agreement with moiré measurements. In the limiting case where the shear modulus of the encapsulant is very low, the model converges to Hall's axisymmetric model for conventional LCCC assemblies. The analysis also gives interfacial stress distributions, a useful feature to assess whether the encapsulant/die and substrate interfaces are overstressed. Various parametric studies are conducted showing that the encapsulant modulus must be high enough to provide adequate strain relief in the solder joints, in agreement with experimental results and advanced finite element studies. Increasing the encapsulant modulus stiffens the assembly, because of mechanical coupling between the die and substrate, but the increased stiffness is overshadowed by much larger reductions in the solder joint strains. The second example is that of a micro-BGA construction where a compliant elastomer layer provides for decoupling between the die and substrate. The package is modeled as a multilayer structure (dielectric film/elastomer/die) where the low modulus elastomer layer behaves like an adhesive bond in shear. The analysis enables tailoring the compliant layer (modulus and thickness) to achieve targeted assembly reliability goals. Both mechanical models capture the reliability impact of the design parameters and materials in a quantitative manner. They can be easily implemented as PC-based design-for-reliability tools to conduct parametric studies on chip, board and assembly parameters.
10:35 am BREAK
10:45 am INVITED
QUALIFICATION TEST FOR SOLDER ATTACHMENT OF CHIP-SCALE BGA PACKAGING: Vern Solberg, Tessera Inc., 3099 Orchard Drive, San Jose, CA 95134
Chip-scale package family for silicon products can be combined to help the engineer and designer meet the most demanding goals for electronic miniaturization,. The significant advantage to employing the miniature Chip-Scale Packaging (CSP) technology is three-fold: higher component density, more efficient assembly automation and enhanced product performance. Bare or unpacked die may be considered for miniaturization, however, a significant advantage a packaged device has over bare die is the ability to test and screen the product before surface mount technology, chip-scale BGA devices have proved efficient, rugged and easily adapted to existing high volume SMT manufacturing processes. Of primary concern to anyone utilizing a new technology is finished product reliability. In this paper, the author will describe several chip-scale device structures, the operational environments they are expected to withstand and the results of, long-term thermal stress testing of the 46 I/O µBGA Flash Memory packages that have been reflow solder attached to conventional laminated circuit structures. Topics covered include: Standards for CSP Technology, Assembly Process Methods, Defining Product Use Environment, Planning the Assembly Test Strategy. Although many of the products being introduced in the miniature chip scale package are compatible with existing surface mount assembly processes, the contact size and pitch are relatively small. And although high assembly yields have been achieved, developing a reliable product using chip-scale devices requires uniform solder paste printing and continued assembly process monitoring.
11:10 am INVITED
RELIABILITY OF ENCAPSULATED SYSTEMS FOR FLIP-CHIP ASSEMBLIES: Cindy M. Melton, Daniel R. Gamota, Motorola, Interconnect & Assembly Technology Research Group, Corporate Manufacturing Research Center, Room 1014, 1301 East Algonquin Road, Schaumburg, IL 60196
Encapsulant materials for flip chip on board assemblies were developed to address the issues of thermal mismatch between the various materials used in this assembly methodology. Several experimental encapsulant materials with enhanced flow properties, shorter cure schedules, and lower stresses have been studied for their effect on manufacturability and their behavior as a compliant structure surrounding the solder joints. Materials characterization studies were performed on the various encapsulants to determine the glass transition temperatures (Tg), tensile elastic and loss modulii (E' and E''), flow profiles, coefficients of thermal expansion (CTE), radii of curvature, stress relaxation as functions of temperature and moisture, and apparent strengths of adhesion. In addition, reliability tests were conducted using FR4 substrates populated with die and underfilled with the various encapsulants to determine the relationship between materials properties and, package and solder joint reliability responses.
11:35 am INVITED
DESIGN OF FLIP-CHIP MCM/BGA PACKAGING FOR OPTIMUM SOLDER JOINT RELIABLITY: T. Dixon Dudderar, Yinon Degani, B. J. Han, V. Reddy Raju, Lucent Technologies, 700 Mountain Avenue, Room 1A-105, Murray Hill, NJ 07974
It is well recognized that the thermal strains associated with material incompatibilities have been the root cause of many failures in both single chip microelectronic packages and in their soldered connections to circuit boards, etc. In so far as solder joints are concerned, flip chip interconnections and the joints under unleaded packages such as BGAs are in many ways "worst case" examples. This paper will describe in detail the unique choices of materials properties and encapsulation structure designed to provide a flip-chip soldered Multichip Module in a BGA package qualified for commercial telephone applications which was both highly reliable and cost effective.
NANOSTRUCTURAL ANALYSIS OF PADS-TREATED SOLDER SURFACE: James L. Marshall and Brett Piekarski, Department of Chemistry, University of North Texas, Denton, TX 76203-5068; Army Research Laboratory, AMSRL-EP-RC, 2800 Powder Mill Road, Adelphi, MD 20783
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