An Article from the June 2004 JOM: A Hypertext-Enhanced Article

Warren H. Hunt, Jr. is a technical consultant at TMS.

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Global Perspectives on Electronic Materials: Challenges and Opportunities

Warren H. Hunt, Jr.

Worldwide cooperation is necessary for continued progress in electronic materials to meet the increasing demands of the information technology age. To stay on the current trajectory of performance improvement, fundamental technology barriers must be overcome to further increase memory capacity and microprocessor speed while simultaneously driving down cost. This article describes several global initiatives to promote advancement in electronic materials technologies.


Electronic materials technology has been the engine of the current information technology age, underlying worldwide economic growth and productivity. In 1965, Gordon E. Moore envisioned the role of integrated electronics in enabling home computers, large-scale communications systems, cell phones, and other products that are commonplace today.1 Likewise, substantial manufacturing productivity gains with a smaller workforce have been possible through the integration of information technology broadly through factory systems, automation, and networks as well as via intelligent manufacturing devices such as computer numerical controlled machine tools and robotics. In the United States, the percentage of manufacturing jobs in the total workforce has declined from roughly 30% to just 15% over the past 50 years, while manufacturing productivity has increased and overall manufacturing output remained constant.2 Sustaining this dramatic progress requires relentless pursuit of new generations of electronic products.


Table I. ITRS Technology Nodes and Chip Capabilities





DRAM half-pitch (nanometers)
DRAM memory size (gigabits)
DRAM cost/bit (micro-cents)
Microprocessor physical gate length (nanometers)
Microprocessor speeds (GHz)

Source: Semiconductor Industry Association

The electronic materials industry has a long history of product improvement. The widely quoted relationship for integration level of the number of components per chip doubling every 24 months that is known as Moore’s Law has been realized for many decades. Coupled with decreasing cost per function, remaining on this track through decreasing the minimum feature sizes used in integrated circuits drives ongoing technological improvement. Defining technological targets and identifying potential roadblocks to achieving those targets has been an area of worldwide cooperation. The International Technology Roadmap for Semiconductors (ITRS)3 has developed a consensus set of targets that permeates the R&D efforts to meet both near-term and long-term objectives.

Table I provides a summary of the main targets, called Technology Nodes in the ITRS, through 2018. The table shows that critical dimension sizes in memory and microprocessors will need to decrease dramatically to stay on the current trajectory of performance improvement. The dynamic random-access memory (DRAM) half-pitch correlates to the width and space in between metal lines connecting DRAM bit cells. The smaller this value, the more DRAM bit cells can fit in a given area. This, in turn, relates to the capacity of the DRAM memory, expressed as gigabits in Table I, and DRAM cost/bit. A second key dimension addressed in the ITRS is the microprocessor physical gate length, which refers to the length of the gate that controls the flow of mobile charges in the underlying silicon as a switch. The shorter the gate length, the faster the switch time becomes, with faster microprocessor speeds, as shown in Table I. The Semiconductor Industry Association notes that achieving the technology targets defined by the ITRS would result in microprocessors that are three times faster by the end of the decade and 12 times faster by 2018. Likewise, memory costs would be 1/8th of today’s cost in 2010 and 1/100th only 8 years later.4


The process of technology roadmapping is one that has seen increasing emphasis as a result of the double demands of speed of innovation and economic streamlining.4 An active roadmapping effort over 15 years in the semiconductors area demonstrates the evolution of the process in response to external stimuli. The 2003 edition of the International Technology Roadmap for Semiconductors builds on a history of roadmaps developed by the Semiconductor Industry Association in the form of the U.S. National Technology Roadmap for Semiconductors in 1992, 1994, and 1997. The 1990s saw the semiconductor industry become increasingly global, and in 1999, through the involvement of international industry associations from Europe, Korea, Taiwan, and Japan, the first international edition was published.

The roadmap is developed through the efforts of 13 Technology Working Groups covering areas typical of the sub-activities that span the product flow for integrated circuits, termed Focus Groups, and important supporting activities that overlap with the product flow at multiple critical points, termed Crosscut Groups. Nearly 1,000 people participate in the Technology Working Groups and represent a broad cross section of organizations, as noted in Figure Aa, with global representation (Figure Ab).

The International Technology Roadmap for Semiconductors (ITRS) presents an industry-wide consensus on the best current estimate of the industry’s R&D needs out to a 15-year time horizon. A basic premise of the roadmap has been that continued scaling of microelectronics would further reduce the cost per function and promote market growth. The roadmap is geared toward identifying the technical challenges that must be overcome to keep pace with Moore’s Law and other trends. Attainment of the targets will push the fundamental limits of materials and require new processes for their manufacture. Advancements necessary are captured in the ITRS in the form of grand challenges. These are divided into two major categories of enhancing performance and cost-effective manufacturing, which are further divided into time frames of near term (up through 2008) and long term (2009–2018).

How successful has the ITRS been for the semiconductor industry? Quoting from the executive summary of the 2003 ITRS, “(i)n the last few years, the ITRS documents have become a truly common reference for the entire semiconductor industry. Indeed, the cooperative efforts of the ITRS participants have fostered cooperation among international consortia, universities, and research institutions around the world. It is hoped that the 2003 ITRS will further contribute to stimulate cooperative R&D investments so that the financial burden can be more uniformly shared by the whole industry. It is also hoped that the 2003 ITRS will continue to stimulate the fundamental elements that encourage innovation in individual companies.”

Globalization, collaboration, innovation . . . the experience of the International Technology Roadmap for Semiconductors has much to teach in all areas of market-driven materials technology development.

Figure A. The composition of the technology group—936 global participants.



Clearly there is significant worldwide collaboration in the semiconductor area. Evidence is the joint activity in the development of the International Technology Roadmap for Semiconductors as well as the evolution of industrial cooperation through what is now known as International SEMATECH, the latter having started as a solely U.S.-government-leveraged activity.

Figure B provides a perspective on the global dimension of the electronic materials field. This figure shows the consumption of semiconductors and indicates the dominant role of the Asia Pacific region since 2001. Manufacturing is routinely carried out on a global basis, with labor cost often being the driver. Research and development activities are also beginning to migrate, with increasing emphasis on processing research in Asian countries. While fundamental material R&D is still focused primarily in the United States and Europe, there is growth in this area in Asian countries as well.

Looking to the future, continued development of worldwide R&D capabilities coupled with manufacturing in the electronics area may bring about fundamental changes. A recent report2 describes the concept of innovation ecosystems consisting of basic R&D, pre-competitive development, prototyping, product development, and manufacturing in which successful avenues of R&D are assisted by the proximity of the manufacturing processes. The report notes that locations that possess strong R&D facilities as well as manufacturing capabilities are expected to have a competitive edge in innovation. A key component of the ecosystem is the human element as a connection between research and manufacturing. The availability of plentiful educated and skilled workers has been a primary competitive advantage for the United States, but this advantage erodes as the quality of academic and training programs in other countries improves.

While this innovation ecosystem model applies to any manufacturing sector, it is considered especially relevant to the information technology area partly because of the short development cycle times and the greater benefit of proximity. Nevertheless, just as the electronics area tends to lead many development trends in the product area, so too does it provide an early view of the changing world order for innovation globally. Nations that are capable of not only manufacturing commodity products with low-cost labor but developing the fundamental capacity for the full spectrum from R&D to manufacturing will compete for technology leadership through innovating new products and new industries. Increasingly we can expect to see multinational companies establish not only their manufacturing plants but also R&D and design centers on an increasingly global basis, changing the industrial ecology as well.

Figure B. The percentage share of gobal semiconductor consumption.

It is apparent from this background that the size of key dimensions on the chip, known as scaling in the semiconductor field, drives performance. It is the dramatic progress in scaling that creates many of the near-term and longer-term technical challenges. For example, creating lithography masks capable of producing the patterns on the chips with 1–2 nm resolution is increasingly challenging and costly. It is projected that 10 years from now, optical lithography will be incapable of producing the desired critical dimensions. Alternative next-generation lithography techniques, such as extreme-ultraviolet, electron-projection, and mask-less, will be needed, with the accompanying costs of replacing the current optical lithography infrastructure. In addition, advanced metrology techniques are needed to measure the fine-scale features.

In the gate area, new gate stack processes and related raw materials will be required as the physical thickness of the gate approaches 1 nm, driven by the need to suppress current leakage in oxynitride films and the substitution of metal gates for the current silicon dioxide/poly-silicon combination. Interconnections between the finer-scale components on a chip and the outside world will be increasingly challenging. Low κ (i.e., low dielectric constant) materials with sufficient mechanical integrity to survive integration processes will be needed. Coupling with the copper interconnects and issues such as adhesion at interfaces and diffusion need to be addressed. In addition, connecting 90 nm and smaller features on the chip to larger-scale components in the outside world requires approaches that will maintain the required levels of accuracy and reliability. As the feature density approaches 107 /chip, new methods will be needed. Optical interconnects were projected to be one answer to this problem, but this is a vision that has not been realized. Microphotonic interconnects are envisioned as a solution that can utilize the silicon infrastructure, while radio frequency (RF) or microwave interconnection schemes have been proposed for the longer term.

One of the key conclusions of the ITRS is that the fundamental limits of materials and processes used in the planar complementary metal-oxide semiconductor (CMOS) structure will be reached in the longer term. While extension of the technology is expected through a number of enhancements, radically different approaches are being investigated. Under consideration are nanomaterials structures such as nanotubes and nanowires, quantum dots, and molecular structures. These are described in more detail in the accompanying article by Rittner in this issue. One clear implication of these approaches would be a change in manufacturing paradigm from the so-called top-down approach involving lithography to a bottoms-up, atom-by-atom assembly process.

While the speed and memory capabilities of chips are often the focus of technology development and newspaper headlines, the packaging of the chip is also an important, if sometimes neglected, aspect. The ITRS recognizes the need for concurrent design at the chip and package levels, driven by short design cycle times. Key packaging considerations include electrical characteristics, thermal dissipation, thermomechanical stress, and cost. Thermal management is becoming an increasingly critical issue as devices shrink and power consumption increases. Current passive cooling techniques dependent on the thermal dissipation of the packaging materials may not be adequate in the future, necessitating active cooling methods and associated cost, complexity, weight, and volume challenges.


Environment, safety, and health (ESH) issues are becoming an increasing focus in the electronic materials area, and impact both current and future material and process choices and development. With the rapid introduction of new chemicals, materials, and processes, assessment methodologies are needed to ensure that ESH impacts are minimized. While currently the industry is in a reactive stance in this area, more proactive efforts and an ESH-design focus for future materials and processes is envisioned. One specific example of the kind of proactive consideration of these issues needed is the accompanying article by Murr et al. on the evaluation of nanomaterials in the environment and potential health implications.

Environment, safety, and health issues are also important in the packaging area. The Restriction of Hazardous Substances (RoHS), set to go into effect in the European Union in July 2006, is driving the elimination of lead from electronic components. One area that has been the focus of significant R&D has been in the area of lead-free solders. A series of articles in this issue addresses some of the materials and processing issues related to the Sn-Ag-Cu system. Also, the development of halogen-free polymer materials that eliminate brominated flame-retardant substances in sealants and printed wiring boards has been an area of focus and substitutions are expected in Japan and Europe.


The ITRS highlights materials modeling as a grand challenge focusing on the modeling of processing and electrical properties of new materials. It notes that “new materials need to be introduced due to physical limits which otherwise would prevent further scaling. Computational materials science needs to be developed and applied to contribute to the assessment and selection of new materials in order to reduce the experimental effort.”

The modeling challenge is increased by the system complexity at the assembly and packaging level. An example of the complexity of systems involved is the joining of metal, organic, and dielectric materials systems that must adhere during the solder-reflow process. With diverse materials having different coefficients of thermal expansion and solders that are heated to 0.9 Tm or higher during the process, accommodating the resulting thermal stresses becomes a significant challenge. New solder systems that have reflow temperatures roughly 30°C above current systems will add new challenges, especially since current solders are fully liquid at these temperatures. Alternatives such as metal-filled polymers are being considered, but key questions regarding their electrical properties, especially in RF systems, are yet to be answered.

Modeling of the thermal and stress performance of the package is also important. For example, heat transfer between the chip and package is critical to optimize materials and design to keep active areas of the chip cool enough to function properly. Also, it is increasingly important in RF and mixed-signal applications, where the inductance and capacitance of interconnections are important design parameters. While modeling can be a useful guide in these problems, the complexity of the requirements involved still necessitates extensive experimental testing and verification for commercial systems.


The semiconductor industry is a research-intensive one. Traditionally, this industry has invested roughly 15% of sales in R&D, and the recent Battelle R&D forecast5 projects that $15.42 billion will be spent in the United States alone in R&D in 2004. Much of the spending is on the shorter-term development work carried out by industry. One approach to meeting the near-term development needs is industrial consortia such as International SEMATECH, with the goal of ensuring the timely availability of the materials, tools, and technology needed to meet the ITRS objectives. Current International SEMATECH efforts involve six key focus areas of 157 nm lithography, mask cost and availability, next-generation lithography, low κ dielectrics, future gate stack, and manufacturing effectiveness. These pre-competitive programs track with the near-term ITRS objectives.

Longer-term needs of the semiconductor industry have traditionally been addressed through cooperation between industry, the academic community, and government. With the ITRS recognition that current semiconductor device technology will reach its limits in 10–15 years, research in fundamental device physics and properties of new materials have increasing urgency. Universities play an important role in providing fundamental knowledge to address future needs, and nearly half a billion dollars have been spent on university research over the past two decades.6 Research at universities in the United States is coordinated through the Focus Center Research Program. The objective of this program is to concentrate attention and resources on areas of microelectronics research that must be addressed to maintain the historic productivity growth curve of the industry. Currently, 31 U.S. universities are involved in five Focus-Center areas related to the ITRS, specifcally interconnects; design and test; materials, structures, and devices; circuits, systems, and software; and nanomaterials. In addition to generating new research results, the program is intended to strengthen the university research infrastructure and expand its capabilities in silicon-related research.


The materials specialist has an especially challenging assignment in the electronic materials world. While the overarching paradigm that chemistry and processing combine to produce microstructure, which in turn determines properties and performance, certainly holds, electronic materials systems present extreme challenges based on the complexity and small length scales of the system, the diversity of material requirements ranging from mechanical to thermal to electrical, and the dual drivers of a short development time scale and focus on cost. As a result, modeling and simulation generally are an integral part of the design and manufacturing process. Electronic materials specialists, therefore, are involved in a dynamic, entrepreneurial environment. Working within the short development cycle encourages the materials specialist to respond quickly and collaborate to obtain needed information. This model is increasingly relevant in the more traditional materials areas, where product development cycle times are also decreasing.


An initial inspiration for this article was the JOM Roundtable of nine years ago titled “Experts Consider the Future of Electronic Materials” [JOM, 47 (3) (1995), pp. 64–65.] The author appreciates the insights provided by a number of TMS members with expertise in electronic materials, including some who were featured in the 1995 article. Specifically, input was provided by:


A significant event each year in the electronic materials R&D community is the TMS-sponsored Electronic Materials Conference (EMC). The 46th meeting, planned for June 23–25 at Notre Dame University, promises to provide a dynamic forum for presentation and discussion of topics in areas related to the preparation and characterization of electronic materials.

Conference General Chair April Brown, a professor at Duke University, describes the EMC as a conference that “addresses the needs of the electronic materials community by creating a forum for the highest quality research in a broad range of topical areas. The conference is unique in its breadth and quality, and in the engagement of students.” The high-quality technical program will offer 260 papers (selected from nearly 400 submitted abstracts) divided into three primary focus areas: issues for wide bandgap materials, nanoscale science and technology in materials, and additional topic areas.

Program Chair Edward Yu, a professor at of the University of California, San Diego, notes that “among the highlights of the conference will be sessions on advanced gate metals and dielectrics for nanoscale CMOS technology including invited presentations from leading researchers at IBM and Intel, joint sessions with the Device Research Conference (DRC) on molecular electronics and flexible electronics, a dedicated session on advances in electron microscopy, and presentations on the latest advances in wide bandgap transistors and light emitters.” Reviewing the program in more detail, the Issues for Wide Bandgap Materials topic includes sessions on nitrides, silicon carbide, and defects and doping. The Nanoscale Science and Technology in Materials sessions address a wide range of materials concepts including quantum dots, wires, wells, molecular electronics, thin-film structures, nanotubes and nanowires along with their characterization and implementation in devices such as sensors. The additional topic areas comprise 13 separate sessions addressing processing, characterization, and integration aspects including epitaxy, non-destructive testing, silicon integration, wafer bonding and alternative substrates, silicon-based heterojunctions, and conventional semiconductor materials.

Perhaps as important as the technical program to the success of this conference are the opportunities provided for interaction and networking with the expected 500 or so attendees from different organizations and countries. “We can expect a mixture of active researchers in industry and university and a high degree of student participation,” notes Brown. A welcoming reception and conference banquet, as well as the stimulating venue of a university campus, all contribute to this benefit.

In addition to the EMC program, the DRC, which focuses on new and exciting breakthroughs and advances in the field of device research, will be held earlier in the same week, with an overlap session with the EMC planned. Also, an exhibition of related products and services will be held. While there is no separate proceedings volume, publication of papers from the conference in the peer-reviewed Journal of Electronic Materials and TMS Letters is planned. Further information on the EMC is available from TMS at or by calling TMS Meeting Services at (724) 776-9000, ext. 243.


1. G.E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics, 38 (8) (April 19, 1965), moorespaper.pdf
2. “Sustaining the Nation’s Innovation Ecosystems, Information Technology Manufacturing and Competitiveness,” President’s Council of Advisors on Science and Technology (16 January 2004),
3. International Technology Roadmap for Semiconductors (San Jose, CA: Semiconductor Industry Association, 2003), Home2003.htm
4. The International Technology Roadmap for Semiconductors (San Jose, CA: Semiconductor Industry Association, January 27, 2004),
5. “2004 R&D Funding Forecast,” R&D Magazine (January 2004), pp. F1–F15.
6. G. Scalise, “Crisis in Research and Development Rx for Economic Health? Money for R&D,” San Francisco Chronicle (24 October 2002).

For more information, contact W.H. Hunt, Jr., TMS, 184 Thorn Hill Road, Warrendale, PA 15086; email:

Copyright held by The Minerals, Metals & Materials Society, 2004

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